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51. 发明申请

US20050054166A1 Conductive metal oxide gate ferroelectric memory transistor 失效
标题翻译：导电金属氧化物栅极铁电存储晶体管
公开(公告)号：US20050054166A1
公开(公告)日：2005-03-10
申请号：US10659547
申请日：2003-09-09
申请人： Sheng Hsu , Tingkai Li
发明人： Sheng Hsu , Tingkai Li
IPC分类号： H01L27/105 , G11C11/22 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L29/78
CPC分类号： G11C11/22 , H01L21/28273 , H01L21/28291 , H01L29/66545 , H01L29/66553 , H01L29/66825 , H01L29/6684 , H01L29/78391
摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.
摘要翻译：本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。

52. 发明申请

US20070284575A1 Metal/semiconductor/metal current limiter 有权
标题翻译：金属/半导体/金属限流器
公开(公告)号：US20070284575A1
公开(公告)日：2007-12-13
申请号：US11893402
申请日：2007-08-15
申请人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
发明人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
IPC分类号： H01L29/12
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).
摘要翻译：提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

53. 发明申请

US20070170536A1 Liquid phase epitaxial GOI photodiode with buried high resistivity germanium layer 审中-公开
标题翻译：液相外延GOI光电二极管，埋置高电阻率锗层
公开(公告)号：US20070170536A1
公开(公告)日：2007-07-26
申请号：US11339011
申请日：2006-01-25
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L31/00
CPC分类号： H01L31/1055 , H01L31/1808 , H01L31/1872 , Y02E10/50
摘要： A device and associated method are provided for fabricating a liquid phase epitaxial (LPE) Germanium-on-Insulator (GOI) photodiode with buried high resistivity Germanium (Ge) layer. The method provides a silicon (Si) substrate, and forms a bottom insulator overlying the Si substrate with a Si seed access area. Then, a Ge P-I-N diode is formed with an n +-doped (n+) mesa, a p+-doped (p+) Ge bottom insulator interface and mesa lateral interface, and a high resistivity Ge layer interposed between the p+ Ge and n+ Ge. A metal electrode is formed overlying a region of the p+ Ge lateral interface, and a transparent electrode is formed overlying the n+ Ge mesa. In one aspect, the method deposits a silicon nitride layer temporary cap overlying the high resistivity Ge layer, and an annealing is performed to epitaxially crystallize the Ge bottom interface and high resistivity Ge layer.
摘要翻译：提供了一种用于制造具有埋置的高电阻率锗（Ge）层的液相外延（LPE）绝缘体锗绝缘体（GOI）光电二极管的器件和相关方法。该方法提供硅（Si）衬底，并且形成具有Si种子存取区域的覆盖Si衬底的底部绝缘体。然后，形成具有n +掺杂（n +）台面，p +掺杂（p +）Ge底部绝缘体界面和台面侧面界面的Ge P-I-N二极管，以及插入在p + Ge和n + Ge之间的高电阻率Ge层。在p + Ge侧面界面的区域上形成金属电极，形成覆盖n + Ge台面的透明电极。在一个方面，该方法沉积覆盖高电阻率Ge层的氮化硅层临时盖，并进行退火以使Ge底界面和高电阻率Ge层外延结晶。

54. 发明申请

US20070141744A1 Method of fabricating a low, dark-current germanium-on-silicon pin photo detector 有权
标题翻译：制造低，暗电流硅 - 硅引脚光电探测器的方法
公开(公告)号：US20070141744A1
公开(公告)日：2007-06-21
申请号：US11312967
申请日：2005-12-19
申请人： Jong-Jan Lee , Douglas Tweet , Jer-Shen Maa , Sheng Hsu
发明人： Jong-Jan Lee , Douglas Tweet , Jer-Shen Maa , Sheng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L31/105 , H01L31/1808 , H01L31/1864 , Y02E10/50 , Y02P70/521 , Y10S438/933
摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the born-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.
摘要翻译：制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在天然掺杂锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火激活N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

55. 发明申请

US20070108502A1 Nanocrystal silicon quantum dot memory device 审中-公开
标题翻译：纳米晶硅量子点存储器件
公开(公告)号：US20070108502A1
公开(公告)日：2007-05-17
申请号：US11281955
申请日：2005-11-17
申请人： Tingkai Li , Sheng Hsu , Lisa Stecker
发明人： Tingkai Li , Sheng Hsu , Lisa Stecker
IPC分类号： H01L29/788 , H01L21/336 , G11C16/04
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/349 , G11C16/3495 , G11C2216/08 , H01L29/15 , H01L29/40114 , H01L29/42324 , H01L29/4925 , H01L29/66825
摘要： A nanocrystal silicon (Si) quantum dot memory device and associated fabrication method have been provided. The method comprises: forming a gate (tunnel) oxide layer overlying a Si substrate active layer; forming a nanocrystal Si memory film overlying the gate oxide layer, including a polycrystalline Si (poly-Si)/Si dioxide stack; forming a control Si oxide layer overlying the nanocrystal Si memory film; forming a gate electrode overlying the control oxide layer; and, forming source/drain regions in the Si active layer. In one aspect, the nanocrystal Si memory film is formed by depositing a layer of amorphous Si (a-Si) using a chemical vapor deposition (CVD) process, and thermally oxidizing a portion of the a-Si layer. Typically, the a-Si deposition and oxidation processes are repeated, forming a plurality of poly-Si/Si dioxide stacks (i.e., 2 to 5 poly-Si/Si dioxide stacks).
摘要翻译：已经提供了纳米晶体硅（Si）量子点存储器件和相关的制造方法。该方法包括：形成覆盖Si衬底有源层的栅极（隧道）氧化层; 形成覆盖栅极氧化物层的纳米晶Si记忆膜，包括多晶Si（多晶硅）/二氧化硅叠层; 形成覆盖在纳米晶Si记忆膜上的对照Si氧化物层; 形成覆盖所述控制氧化物层的栅电极; 并且在Si有源层中形成源/漏区。在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层（a-Si）并热氧化a-Si层的一部分来形成纳米晶体Si记忆膜。通常，重复a-Si沉积和氧化过程，形成多个多Si /二氧化硅叠层（即2至5个多硅/二氧化硅叠层）。

56. 发明申请

US20070015330A1 Metal/semiconductor/metal (MSM) back-to-back Schottky diode 有权
标题翻译：金属/半导体/金属（MSM）背对背肖特基二极管
公开(公告)号：US20070015330A1
公开(公告)日：2007-01-18
申请号：US11435669
申请日：2006-05-17
申请人： Tingkai Li , Sheng Hsu , David Evans
发明人： Tingkai Li , Sheng Hsu , David Evans
IPC分类号： H01L21/8242
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
摘要翻译：提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。通常，响应于Si厚度的增加，阈值和击穿电压都增加。关于开/关电流比，存在最佳厚度。该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

57. 发明申请

US20070015328A1 MSM binary switch memory device 有权
公开(公告)号：US20070015328A1
公开(公告)日：2007-01-18
申请号：US11184660
申请日：2005-07-18
申请人： Sheng Hsu , Tingkai Li
发明人： Sheng Hsu , Tingkai Li
IPC分类号： H01L21/8242
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

58. 发明申请

US20070001163A1 Floating body germanium phototransistor 有权
标题翻译：浮体锗光电晶体管
公开(公告)号：US20070001163A1
公开(公告)日：2007-01-04
申请号：US11174035
申请日：2005-07-01
申请人： Jong-Jan Lee , Sheng Hsu , Jer-Shen Maa , Douglas Tweet
发明人： Jong-Jan Lee , Sheng Hsu , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L31/00
CPC分类号： H01L31/1136 , H01L31/028 , H01L31/1808 , Y02E10/547
摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.
摘要翻译：提出了一种浮体锗（Ge）光电晶体管及其制造工艺。该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

59. 发明申请

US20060194403A1 PCMO thin film with controlled resistance characteristics 审中-公开
标题翻译： PCMO薄膜具有受控电阻特性
公开(公告)号：US20060194403A1
公开(公告)日：2006-08-31
申请号：US11378719
申请日：2006-03-17
申请人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： H01L21/20
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1
摘要翻译：已经提供了具有预定的记忆电阻特性和相关的形成过程的PrCaMnO（PCMO）薄膜。在一个方面，所述方法包括：形成Pr 3+ 1-x 2 Ca 2 O 3 x MnO薄膜组成，其中0.1 _0.78Mn^{4+</SUP>_0.22O^2-_{2.96 组合， Mn和O离子的比例变化如下：O 2 - （2.96）; Mn（3+）+（（1-x）+ 8％）; 和Mn 4+（x-8％）。在另一方面，该方法响应于晶体取向在PCMO膜中产生密度。例如，如果PCMO膜具有（110）取向，则在垂直于（110）取向的平面中产生在每平方英尺5至6.76个Mn原子的范围内的密度。}}

60. 发明申请

US20060189151A1 Method for forming an infrared photodetector with a vertical optical path 审中-公开
标题翻译：用于形成具有垂直光路的红外光电探测器的方法
公开(公告)号：US20060189151A1
公开(公告)日：2006-08-24
申请号：US11384121
申请日：2006-03-17
申请人： Douglas Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Hsu
发明人： Douglas Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Hsu
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L31/035281 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/0265 , H01L31/101 , H01L31/1812 , Y02E10/50
摘要： Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and, selectively forming a SiGe optical path overlying the Si normal feature. In some aspects, the Si substrate surface is formed a first plane and the Si normal feature has walls (sidewalls), normal with respect to the Si substrate surface, and a surface in a second plane, parallel to the first plane. Then, selectively forming a SiGe optical path overlying the Si normal feature includes forming a SiGe vertical optical path overlying the normal feature walls.
摘要翻译：提供了SiGe垂直光路和用于选择性地形成用于IR光电检测的SiGe光路法线结构的方法。该方法包括：形成Si衬底表面; 形成Si特征，相对于诸如沟槽，通孔或支柱的Si衬底表面是正常的; 并且选择性地形成覆盖Si正常特征的SiGe光路。在一些方面，Si衬底表面形成第一平面，并且Si正常特征具有相对于Si衬底表面法线的壁（侧壁）和平行于第一平面的第二平面中的表面。然后，选择性地形成覆盖Si正常特征的SiGe光路包括形成覆盖正常特征壁的SiGe垂直光路。

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