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51. 发明授权

US06920553B1 Method and apparatus for reading initial boot instructions from a bootable device connected to the USB port of a computer system 有权
标题翻译：从连接到计算机系统的USB端口的可引导设备读取初始引导指令的方法和装置
公开(公告)号：US06920553B1
公开(公告)日：2005-07-19
申请号：US09560858
申请日：2000-04-28
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G06F9/00 , G06F9/445
CPC分类号： G06F9/4401 , G06F11/1417
摘要： In one embodiment, a design is described for providing the BIOS instructions to a computer through the USB port. At boot-up, a USB controller checks the USB port for a bootable device containing BIOS instructions. If a bootable device is connected, the USB controller transfers the BIOS instructions through the USB port to the processor. The computer then boots-up using the USB boot instructions. If no bootable device is connected to the USB port, the computer looks to a standard BIOS EPROM for boot instructions.
摘要翻译：在一个实施例中，描述了通过USB端口向计算机提供BIOS指令的设计。在启动时，USB控制器检查USB端口是否包含BIOS指令的可引导设备。如果连接了可引导设备，则USB控制器将BIOS指令通过USB端口传输到处理器。然后，计算机使用USB启动指令启动。如果没有可启动设备连接到USB端口，则计算机将查看标准BIOS EPROM以获取引导说明。

52. 发明授权

US06795884B2 Read-only memory based circuitry for sharing an interrupt between disk drive interfaces 失效
标题翻译：只读存储器的电路，用于在磁盘驱动器接口之间共享中断
公开(公告)号：US06795884B2
公开(公告)日：2004-09-21
申请号：US09751272
申请日：2000-12-29
申请人： David I. Poisner , Louis A. Lippincott
发明人： David I. Poisner , Louis A. Lippincott
IPC分类号： G06F1324
CPC分类号： G06F9/3891 , G06F9/30043 , G06F9/3824 , G06F9/3828 , G06F9/3867 , G06F9/3885
摘要： An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.
摘要翻译：用于在用于并行存储设备接口的控制器和用于串行存储设备接口的控制器之间共享中断的设备包括：中断调节电路，其屏蔽来自并行存储设备接口的中断信号，如果没有存储设备耦合到并行存储器设备接口没有存储设备的并行存储设备接口中断的屏蔽耦合到并行存储设备接口，允许串行存储设备接口的控制器共享传统分配给并行存储设备接口的中断。

53. 发明授权

US06754840B2 Over-clocking detection system utilizing a reference signal and thereafter preventing over-clocking by reducing clock rate 有权
标题翻译：超时检测系统利用参考信号，然后通过降低时钟速率来防止超频
公开(公告)号：US06754840B2
公开(公告)日：2004-06-22
申请号：US10315156
申请日：2002-12-10
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G06F104
CPC分类号： G06F21/725 , G06F11/00 , G06F11/004
摘要： An over-clock deterrent mechanism of a chipset which comprises an over-clock detection circuit for detecting over-clocking of a system (processor) clock signal based on comparison of ratio of the system (processor) clock signal which is likely to be over-clocked and a fixed, stable reference clock signal which is highly unlikely to be over-clocked, and an over-clock prevention (thwarting) circuit for deterring such an over-clocking by either disabling operations of a computer system or significantly undermining key operations of a computer system.
摘要翻译：一种芯片组的超时钟威慑机制，其包括用于基于比较可能过载的系统（处理器）时钟信号的比率来检测系统（处理器）时钟信号的超频的超时钟检测电路，时钟和固定的稳定的参考时钟信号，这是非常不可能超时的，以及用于通过禁用计算机系统的操作来阻止这种超频的超时钟防止（阻止）电路，或显着地破坏了计算机系统的关键操作一个电脑系统。

54. 发明授权

US06742073B1 Bus controller technique to control N buses 有权
标题翻译：总线控制器技术来控制N总线
公开(公告)号：US06742073B1
公开(公告)日：2004-05-25
申请号：US09746162
申请日：2000-12-26
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G06F1340
CPC分类号： G06F13/42 , G06F13/4004
摘要： A technique for operating a bus controller to control N buses, each bus capable of having at least one device connected thereto, N being an integer greater than 1, includes reading a descriptor inputted to the bus controller and determining from the read descriptor whether a data transfer operation is a read operation or a write operation. The descriptor may indicate whether the device to be accessed is connected to a first bus or a second bus or alternatively, information from the descriptor may be compared with a separate list to determine if the device to be accessed is connected to the first bus or the second bus.
摘要翻译：一种用于操作总线控制器以控制N个总线的技术，每个总线能够具有连接到其上的至少一个设备，N是大于1的整数，包括读取输入到总线控制器的描述符，并从读取的描述符确定数据传送操作是读操作或写操作。描述符可以指示要被访问的设备是否连接到第一总线或第二总线，或者替代地，来自描述符的信息可以与单独的列表进行比较，以确定要访问的设备是否连接到第一总线或者第二班车。

55. 发明授权

US06374321B1 Mechanisms for converting address and data signals to interrupt message signals 有权
公开(公告)号：US06374321B1
公开(公告)日：2002-04-16
申请号：US09428682
申请日：1999-10-27
申请人： Stephen S. Pawlowski , Darren L. Abramson , David I. Poisner , Kishore K. Mishra
发明人： Stephen S. Pawlowski , Darren L. Abramson , David I. Poisner , Kishore K. Mishra
IPC分类号： G06F946
摘要： In some embodiments, the invention includes an apparatus including a host bridge coupled to a processor bus. The apparatus also includes an I/O bridge coupled to the host bridge, the I/O bridge including ports to receive an interrupt request signal in the form of address signals and data signals. Decode logic receives at least some of the address signals and data signals and to provide a decoded signal responsive thereto. A redirection table includes a send pending bit that is set responsive to the decoded signal.

56. 发明授权

US06269443B1 Method and apparatus for automatically selecting CPU clock frequency multiplier 有权
标题翻译：自动选择CPU时钟倍频器的方法和装置
公开(公告)号：US06269443B1
公开(公告)日：2001-07-31
申请号：US09222067
申请日：1998-12-29
申请人： David I. Poisner , Kuljit S. Bains
发明人： David I. Poisner , Kuljit S. Bains
IPC分类号： G06F124
CPC分类号： G06F1/08
摘要： An apparatus for automatically selecting a processor clock frequency multiplier is disclosed. The apparatus includes a reset circuit that transmits a reset signal to a processor. When the reset signal is deasserted, the processor samples the states of various strapping signals that are provided by the apparatus. The states of the various strapping signals are determined by a clock frequency multiplier indicator circuit in the apparatus. The apparatus also includes a processor failure detection unit that determines if the processor fails to function properly after reset. If the processor failure detection unit determines that the processor is not functioning properly, the clock frequency multiplier indicator circuit indicates a smaller clock frequency multiplier and a new reset of the processor is performed by asserting the reset signal. The process is repeated until either the processor is determined to be operating properly or the clock frequency multiplier indicator circuit has indicated the smallest possible clock frequency multiplier.
摘要翻译：公开了一种用于自动选择处理器时钟倍频器的装置。该装置包括将复位信号发送到处理器的复位电路。当复位信号被断言时，处理器对设备提供的各种捆扎信号的状态进行采样。各种捆扎信号的状态由装置中的时钟倍频器指示电路确定。该装置还包括处理器故障检测单元，其确定在复位之后处理器是否能够正常工作。如果处理器故障检测单元确定处理器不能正常工作，则时钟倍频器指示器电路指示较小的时钟倍频器，并且通过置位复位信号来执行处理器的新复位。重复该过程，直到处理器被确定为正常工作或时钟倍频器指示器电路已经指示尽可能小的时钟倍频器。

57. 发明授权

US5862387A Method and apparatus for handling bus master and direct memory access (DMA) requests at an I/O controller 失效
标题翻译：用于在I / O控制器处理总线主控和直接存储器访问（DMA）请求的方法和装置
公开(公告)号：US5862387A
公开(公告)日：1999-01-19
申请号：US884023
申请日：1997-06-27
申请人： Neil W Songer , James P. Kardach , Sung-Soo Cho , Jim S. Cheng , Debra T. Cohen , John W. Horigan , Nader Raygani , Seyed Yahay Sotoudeh , David I. Poisner
发明人： Neil W Songer , James P. Kardach , Sung-Soo Cho , Jim S. Cheng , Debra T. Cohen , John W. Horigan , Nader Raygani , Seyed Yahay Sotoudeh , David I. Poisner
IPC分类号： G06F13/28 , G06F13/30 , G06F13/364 , G06F13/00
CPC分类号： G06F13/28 , G06F13/30 , G06F13/364
摘要： A computer system that implements a direct memory access (DMA) request passing protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. The PCI bus is coupled to at least one DMA agent and a DMA controller. The DMA agent issues DMA requests to the DMA controller using the electrical interface of the PCI bus. According to one embodiment, a system I/O controller receives the DMA requests and passes them on to the DMA controller, which arbitrates the DMA requests and passes back a grant to the system I/O controller. The system I/O controller uses the electrical interface of the PCI bus to pass the grant to the DMA agent. The same DMA request passing protocol may be implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.
摘要翻译：实现直接内存访问（DMA）请求传递协议的计算机系统。计算机系统可以包括外围组件互连（PCI）总线，其包括由PCI本地总线标准指定的电接口。 PCI总线耦合到至少一个DMA代理和DMA控制器。 DMA代理使用PCI总线的电接口向DMA控制器发出DMA请求。根据一个实施例，系统I / O控制器接收DMA请求并将它们传递到DMA控制器，DMA控制器对DMA请求进行仲裁，并将授权传回给系统I / O控制器。系统I / O控制器使用PCI总线的电接口将授权传递给DMA代理。相同的DMA请求传递协议可以在具有为总线的每个总线代理指定唯一请求信号线的电接口的任何总线中实现。

58. 发明授权

US5708815A DMA emulation via interrupt muxing 失效
标题翻译：通过中断复用进行DMA仿真
公开(公告)号：US5708815A
公开(公告)日：1998-01-13
申请号：US437091
申请日：1995-05-05
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G06F13/28 , G06F9/46 , G06F13/14
CPC分类号： G06F13/28
摘要： An apparatus and method for coordinating DMA between memory and a peripheral on a bus which does not support DMA comprises DMA emulation circuitry in the peripheral which allows the internal modules of the peripheral to share a single shared interrupt output line. An emulation device driver assists the microprocessor in determining the cause of interrupt signals received by the shared interrupt output line and how to service the interrupt.
摘要翻译：用于在不支持DMA的总线上协调存储器和外设之间的DMA的装置和方法包括外设中的DMA仿真电路，其允许外设的内部模块共享单个共享中断输出线。仿真设备驱动程序帮助微处理器确定共享中断输出线接收的中断信号的原因以及如何维护中断。

59. 发明授权

US5652895A Computer system having a power conservation mode and utilizing a bus arbiter device which is operable to control the power conservation mode 失效
标题翻译：计算机系统具有省电模式并利用可操作以控制功率节省模式的总线仲裁器装置
公开(公告)号：US5652895A
公开(公告)日：1997-07-29
申请号：US578035
申请日：1995-12-26
申请人： David I. Poisner
发明人： David I. Poisner
IPC分类号： G06F1/32 , G06F13/364
CPC分类号： G06F1/325 , G06F1/3203 , G06F1/3253 , G06F1/3287 , G06F13/364 , Y02B60/1235 , Y02B60/1282
摘要： A digital system bus and its attached devices can be powered down and up using only its standard bus request and bus grant signal lines, without adding additional lines for control signals. By asserting the bus grant signal in the absence of the bus request signal, the bus arbiter device can signal other devices on the bus that is okay to enter a deep power conservation mode. In this mode, the devices on the bus may safely ignore bus activity--except they must monitor for a negation of the bus grant signal or for any system wake-up events for which they are responsible. Substantial power reduction can be achieved in such a mode, since clocks can be suspended to a large portion of the circuitry in the computer system. To wake up the non-arbiter devices, the bus arbiter simply negates the bus grant signal. To wake up the bus arbiter device, a non-arbiter device simply asserts its bus request signal. This deep power conservation mode may be enabled under software control, by means of software writing an enable bit in one or more of the bus devices.
摘要翻译：数字系统总线及其连接的设备可以仅使用其标准总线请求和总线授权信号线进行掉电和上电，而无需为控制信号添加额外的线路。通过在没有总线请求信号的情况下断言总线授权信号，总线仲裁器可以通知总线上可以进入深度功率节省模式的其他设备。在这种模式下，总线上的设备可以安全地忽略总线活动，除非它们必须监视总线授权信号的否定或其负责的任何系统唤醒事件。可以在这种模式下实现大量的功率降低，因为时钟可以被悬挂到计算机系统中的电路的大部分。为了唤醒非仲裁设备，总线仲裁器简单地否定总线授权信号。为了唤醒总线仲裁器，非仲裁设备简单地断言其总线请求信号。通过在一个或多个总线设备中写入使能位的软件可以在软件控制下启用该深度功率节省模式。

60. 发明申请

US20180190024A1 SPACE BASED CORRELATION TO AUGMENT USER EXPERIENCE 审中-公开
公开(公告)号：US20180190024A1
公开(公告)日：2018-07-05
申请号：US15395629
申请日：2016-12-30
申请人： Therese E. Dugan , Katherine E. Mills , Glen J. Anderson , Meng Shi , John Gaffrey , David I. Poisner
发明人： Therese E. Dugan , Katherine E. Mills , Glen J. Anderson , Meng Shi , John Gaffrey , David I. Poisner
IPC分类号： G06T19/00 , G06K9/00
CPC分类号： G06T19/006 , G06K9/00671 , H04N21/816
摘要： Systems, apparatuses, and/or methods to augment a user experience. A correlater may correlate a physical three-dimensional (3D) play space and a setting space of media content. An augmenter may augment the media content based on a change in the physical 3D play space. An augmenter may augment the physical 3D play space based on a change in the setting space.

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