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1. 发明授权

US5862387A Method and apparatus for handling bus master and direct memory access (DMA) requests at an I/O controller 失效
标题翻译：用于在I / O控制器处理总线主控和直接存储器访问（DMA）请求的方法和装置
公开(公告)号：US5862387A
公开(公告)日：1999-01-19
申请号：US884023
申请日：1997-06-27
申请人： Neil W Songer , James P. Kardach , Sung-Soo Cho , Jim S. Cheng , Debra T. Cohen , John W. Horigan , Nader Raygani , Seyed Yahay Sotoudeh , David I. Poisner
发明人： Neil W Songer , James P. Kardach , Sung-Soo Cho , Jim S. Cheng , Debra T. Cohen , John W. Horigan , Nader Raygani , Seyed Yahay Sotoudeh , David I. Poisner
IPC分类号： G06F13/28 , G06F13/30 , G06F13/364 , G06F13/00
CPC分类号： G06F13/28 , G06F13/30 , G06F13/364
摘要： A computer system that implements a direct memory access (DMA) request passing protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. The PCI bus is coupled to at least one DMA agent and a DMA controller. The DMA agent issues DMA requests to the DMA controller using the electrical interface of the PCI bus. According to one embodiment, a system I/O controller receives the DMA requests and passes them on to the DMA controller, which arbitrates the DMA requests and passes back a grant to the system I/O controller. The system I/O controller uses the electrical interface of the PCI bus to pass the grant to the DMA agent. The same DMA request passing protocol may be implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.
摘要翻译：实现直接内存访问（DMA）请求传递协议的计算机系统。计算机系统可以包括外围组件互连（PCI）总线，其包括由PCI本地总线标准指定的电接口。 PCI总线耦合到至少一个DMA代理和DMA控制器。 DMA代理使用PCI总线的电接口向DMA控制器发出DMA请求。根据一个实施例，系统I / O控制器接收DMA请求并将它们传递到DMA控制器，DMA控制器对DMA请求进行仲裁，并将授权传回给系统I / O控制器。系统I / O控制器使用PCI总线的电接口将授权传递给DMA代理。相同的DMA请求传递协议可以在具有为总线的每个总线代理指定唯一请求信号线的电接口的任何总线中实现。

2. 发明授权

US5664197A Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller 失效
标题翻译：用于在I / O控制器处理总线主通道和直接存储器访问（DMA）通道访问请求的方法和装置
公开(公告)号：US5664197A
公开(公告)日：1997-09-02
申请号：US426825
申请日：1995-04-21
申请人： James P. Kardach , Sung-Soo Cho , Jim S. Cheng , Debra T. Cohen , John W. Horigan , Nader Raygani , Seyed Yahay Sotoudeh , David I. Poisner , Neil W. Songer
发明人： James P. Kardach , Sung-Soo Cho , Jim S. Cheng , Debra T. Cohen , John W. Horigan , Nader Raygani , Seyed Yahay Sotoudeh , David I. Poisner , Neil W. Songer
IPC分类号： G06F13/28 , G06F13/30 , G06F13/364 , G06F13/00
CPC分类号： G06F13/28 , G06F13/30 , G06F13/364
摘要： A computer system that implements a direct memory access (DMA) request passing protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. The PCI bus is coupled to at least one DMA agent and a DMA controller. The DMA agent issues DMA requests to the DMA controller using the electrical interface of the PCI bus. According to one embodiment, a system I/O controller receives the DMA requests and passes them on to the DMA controller, which arbitrates the DMA requests and passes back a grant to the system I/O controller. The system I/O controller uses the electrical interface of the PCI bus to pass the grant to the DMA agent. The same DMA request passing protocol may be implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.
摘要翻译：实现直接存储器访问（DMA）请求传递协议的计算机系统。计算机系统可以包括外围组件互连（PCI）总线，其包括由PCI本地总线标准指定的电接口。 PCI总线耦合到至少一个DMA代理和DMA控制器。 DMA代理使用PCI总线的电接口向DMA控制器发出DMA请求。根据一个实施例，系统I / O控制器接收DMA请求并将它们传递到DMA控制器，DMA控制器对DMA请求进行仲裁，并将授权传回给系统I / O控制器。系统I / O控制器使用PCI总线的电接口将授权传递给DMA代理。相同的DMA请求传递协议可以在具有为总线的每个总线代理指定唯一请求信号线的电接口的任何总线中实现。

3. 发明授权

US5729762A Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent 失效
标题翻译：具有耦合到DMA控制器和多个地址线的接口逻辑的输入输出控制器，用于向DMA代理传送控制信息
公开(公告)号：US5729762A
公开(公告)日：1998-03-17
申请号：US426818
申请日：1995-04-21
申请人： James P. Kardach , Sung-Soo Cho , Debra T. Cohen , John W. Horigan , Neil W. Songer
发明人： James P. Kardach , Sung-Soo Cho , Debra T. Cohen , John W. Horigan , Neil W. Songer
IPC分类号： G06F13/28 , G06F15/40
CPC分类号： G06F13/28
摘要： A computer system performs direct memory access (DMA) transfers according to a DMA transfer protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. A DMA agent, system memory, and a DMA controller are coupled to the bus. The DMA controller uses the electrical interface of the PCI bus to control a DMA transfer between system memory and the DMA agent. According to one embodiment, a system I/O controller is coupled between the DMA controller and the PCI bus. The system I/O controller passes DMA control information from the DMA controller to the DMA agent using the electrical interface of the PCI bus. The electrical interface of the PCI bus includes a plurality of address lines and a grant signal line coupled to the DMA agent, wherein the system that I/O controller transmits DMA control information to the DMA agent while asserting the grant signal line.
摘要翻译：计算机系统根据DMA传输协议执行直接存储器访问（DMA）传输。计算机系统可以包括外围组件互连（PCI）总线，其包括由PCI本地总线标准指定的电接口。 DMA代理，系统存储器和DMA控制器耦合到总线。 DMA控制器使用PCI总线的电接口来控制系统内存和DMA代理之间的DMA传输。根据一个实施例，系统I / O控制器耦合在DMA控制器和PCI总线之间。系统I / O控制器使用PCI总线的电接口将DMA控制信息从DMA控制器传送到DMA代理。 PCI总线的电接口包括多个地址线和耦合到DMA代理的授权信号线，其中I / O控制器在断言授权信号线的同时向DMA代理发送DMA控制信息的系统。

4. 发明授权

US5892931A Method and apparatus for splitting a bus target response between two devices in a computer system 失效
标题翻译：用于在计算机系统中的两个设备之间划分总线目标响应的方法和装置
公开(公告)号：US5892931A
公开(公告)日：1999-04-06
申请号：US810690
申请日：1997-02-28
申请人： Debra T. Cohen , Sung-Soo Cho , Chao-Hsin Chi , David Chang
发明人： Debra T. Cohen , Sung-Soo Cho , Chao-Hsin Chi , David Chang
IPC分类号： G06F12/02 , G06F13/40 , G06F13/38
CPC分类号： G06F13/404 , G06F13/4027
摘要： The present invention provides a method and apparatus for splitting a bus target response between two devices in a computer system. In one embodiment, the computer system includes a bus having a first signal line and a second signal line, a third signal line, and two agents coupled to the bus and the third signal line. The first agent claims to be a target of a transaction on the bus without decoding the address associated with the transaction by asserting the first signal on the first signal line. The second agent responds to the transaction as the target. The second agent thereafter asserts a third signal on the third signal line to coordinate deassertion of the first signal on the first signal line by the first agent and concurrent assertion of the second signal on the second signal line by the second agent.
摘要翻译：本发明提供了一种用于在计算机系统中的两个设备之间分割总线目标响应的方法和装置。在一个实施例中，计算机系统包括具有第一信号线和第二信号线，第三信号线以及耦合到总线和第三信号线的两个代理的总线。第一代理人声称是在总线上进行交易的目标，而不通过在第一信号线上断言第一信号来解码与交易相关联的地址。第二代理人作为目标回应交易。第二代理随后在第三信号线上确定第三信号，以协调第一代理在第一信号线上的第一信号的取消取消，并且由第二代理在第二信号线上同时确定第二信号。

5. 发明授权

US07027057B2 Entering and exiting power managed states without disrupting accelerated graphics port transactions 失效
公开(公告)号：US07027057B2
公开(公告)日：2006-04-11
申请号：US10640196
申请日：2003-08-12
申请人： Satchit Jain , Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Anil V. Nanduri
发明人： Satchit Jain , Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Anil V. Nanduri
IPC分类号： G06F13/14 , G06F1/26 , G06F1/32 , G06F13/28 , G09F5/39
CPC分类号： G06T17/00 , G06F1/3203
摘要： An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

6. 发明授权

US06738068B2 Entering and exiting power managed states without disrupting accelerated graphics port transactions 有权
标题翻译：进入和退出电源管理状态，而不会中断加速图形端口事务
公开(公告)号：US06738068B2
公开(公告)日：2004-05-18
申请号：US09751441
申请日：2000-12-29
申请人： Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Satchit Jain , Anil V. Nanduri
发明人： Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Satchit Jain , Anil V. Nanduri
IPC分类号： G06F1314
CPC分类号： G06T17/00 , G06F1/3203
摘要： An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.
摘要翻译：加速图形端口图形控制器（AGP-GC）和核心控制器之间的接口，以防止进入低功率状态，干扰来自AGP-GC的请求但尚未完成的传输。核心控制器可以与AGP-GC进行通信，意图进入低功率状态，而AGP-GC可以与核心控制器通信AGP-GC的忙碌状态。当AGP-GC接收到进入低功率状态的意图时，可以停止向核心控制器发出请求。当核心控制器检测到AGP-GC正忙时，核心控制器可以推迟进入低功率状态，直到AGP-GC完成任何正在进行的请求。在接口的替代使用中，如果AGP-GC希望在低功率状态期间发出请求，则可以通过指示忙状态来向核心控制器通知该核心控制器，这可以触发核心控制器发起退出低功率状态。

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