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51. 发明授权

US07898841B2 Preservation circuit and methods to maintain values representing data in one or more layers of memory 有权
公开(公告)号：US07898841B2
公开(公告)日：2011-03-01
申请号：US12800512
申请日：2010-05-17
申请人： Christophe J. Chevallier , Robert Norman
发明人： Christophe J. Chevallier , Robert Norman
IPC分类号： G11C11/00
CPC分类号： G11C13/0035 , G11C5/005 , G11C5/02 , G11C11/16 , G11C13/0002 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/71 , G11C2213/77
摘要： Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

52. 发明申请

US20100027314A1 Preservation circuit and methods to maintain values representing data in one or more layers of memory 有权
公开(公告)号：US20100027314A1
公开(公告)日：2010-02-04
申请号：US12221136
申请日：2008-07-31
申请人： Christophe J. Chevallier , Robert Norman
发明人： Christophe J. Chevallier , Robert Norman
IPC分类号： G11C11/00 , G06F12/00
CPC分类号： G11C13/0035 , G11C5/005 , G11C5/02 , G11C11/16 , G11C13/0002 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/71 , G11C2213/77
摘要： Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

53. 发明授权

US07457997B2 Apparatus and method for detecting over-programming condition in multistate memory device 失效
标题翻译：多状态存储器件中过度编程条件的检测装置及方法
公开(公告)号：US07457997B2
公开(公告)日：2008-11-25
申请号：US10629279
申请日：2003-07-29
申请人： Robert D. Norman , Christophe J. Chevallier
发明人： Robert D. Norman , Christophe J. Chevallier
IPC分类号： G11C29/00 , G11C16/06 , G11C16/04 , G11C7/00
CPC分类号： G11C29/765 , G06F11/1072 , G11C7/1039 , G11C11/5621 , G11C11/5628 , G11C16/04 , G11C16/3413 , G11C16/3418 , G11C16/3463 , G11C29/00 , G11C29/52 , G11C29/76 , G11C29/82 , G11C2029/0409 , G11C2211/5643
摘要： An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.
摘要翻译：一种用于检测多态存储器单元中的过编程状态的装置和方法。本发明还涉及识别过程编程的单元并提供写入用于过程编程单元的数据的备用位置。当发现包含在多状态存储器单元中的数据相对于其预期编程（阈值电压电平）状态被发现过度编程时，过程编程状态检测电路产生错误信号。在检测到过度编程的单元时，修改存储器系统的编程操作以中止对单元的进一步编程尝试。过度编程状态检测电路还用于帮助校正过度编程状态，允许由存储器系统补偿编程错误。

54. 发明授权

US07236400B2 Erase verify for non-volatile memory using a bitline current-to-voltage converter 有权
标题翻译：使用位线电流 - 电压转换器擦除非易失性存储器的验证
公开(公告)号：US07236400B2
公开(公告)日：2007-06-26
申请号：US11198256
申请日：2005-08-05
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C16/34
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
摘要翻译：存储器件验证系统确定存储器中存储器单元的状态。存储器包括具有耦合到位线的多个存储器单元的存储器阵列。验证电路耦合到位线以确定存储器单元是否具有在预定的上限和下限内的擦除电平。验证电路可以包括第一和第二比较器。在一个实施例中，第一比较器用于将位线电流与较高的第一参考电流进行比较。第二比较器用于将位线电流与较低的第二参考电流进行比较。比较器电路不限于参考电流，但可以使用参考电压与位线电压进行比较。因此，验证电路不需要单独的位线泄漏测试来识别过度擦除的存储器单元。

55. 发明授权

US07230855B2 Erase verify for non-volatile memory using bitline/reference current-to-voltage converters 有权
标题翻译：使用位线/参考电流 - 电压转换器擦除非易失性存储器的验证
公开(公告)号：US07230855B2
公开(公告)日：2007-06-12
申请号：US11198212
申请日：2005-08-05
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C16/34
CPC分类号： G11C16/3404 , G11C16/344
摘要： A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
摘要翻译：存储器件验证系统确定存储器中存储器单元的状态。存储器包括具有耦合到位线的多个存储器单元的存储器阵列。验证电路耦合到位线以确定存储器单元是否具有在预定的上限和下限内的擦除电平。验证电路可以包括第一和第二比较器。在一个实施例中，第一比较器用于将位线电流与较高的第一参考电流进行比较。第二比较器用于将位线电流与较低的第二参考电流进行比较。比较器电路不限于参考电流，但可以使用参考电压与位线电压进行比较。因此，验证电路不需要单独的位线泄漏测试来识别过度擦除的存储器单元。

56. 发明授权

US06845053B2 Power throughput adjustment in flash memory 有权
标题翻译：闪存中的电源吞吐量调整
公开(公告)号：US06845053B2
公开(公告)日：2005-01-18
申请号：US10295653
申请日：2002-11-15
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C16/30 , G11C7/00
CPC分类号： G11C29/028 , G11C16/04 , G11C16/30
摘要： A mode control bit is used to adjust a mode of a memory device. The mode control bit is stored in a non-volatile memory location and selects between a data rate, low power consumption mode and a higher power, fast programming mode. In the low power consumption mode the mode control bit reduces the rate at which data bits are programmed into the memory device.
摘要翻译：模式控制位用于调整存储器件的模式。模式控制位存储在非易失性存储器位置，并在数据速率，低功耗模式和较高功率，快速编程模式之间进行选择。在低功耗模式下，模式控制位降低了将数据位编程到存储器件中的速率。

57. 发明授权

US06788037B2 Voltage converter system and method having a stable output voltage 有权
公开(公告)号：US06788037B2
公开(公告)日：2004-09-07
申请号：US10388053
申请日：2003-03-12
申请人： Christophe J. Chevallier , Dumitru Cioaca
发明人： Christophe J. Chevallier , Dumitru Cioaca
IPC分类号： G05F144
CPC分类号： G05F1/465
摘要： An apparatus and method for compensating for a decreasing internal voltage that is generated from a higher external voltage. In response to the internal voltage decreasing in excess of a voltage margin, the amount by which the higher external voltage is reduced in generating the internal voltage is adjusted to raise the internal voltage.

58. 发明授权

US06760267B2 Segmented non-volatile memory array with multiple sources having improved source line decode circuitry 失效
标题翻译：具有多个源的分段非易失性存储器阵列具有改进的源极线解码电路
公开(公告)号：US06760267B2
公开(公告)日：2004-07-06
申请号：US10174205
申请日：2002-06-17
申请人： Christophe J. Chevallier , Vinod C. Lakhani
发明人： Christophe J. Chevallier , Vinod C. Lakhani
IPC分类号： G11C700
CPC分类号： H01L27/115 , G11C16/08
摘要： A flash memory array arrangement having a plurality of erase blocks which can be separately erased. The erase blocks have separate source lines, the state of which is controlled by a source line decoder. In array read, program and erase operations, the source lines of the deselected erase blocks, the blocks that are not being read, programmed or erased, are set to a high impedance level. If a cell in one of the deselected erase blocks is defective in some respect such that the cell is conducting leakage current, the high impedance source line associated with the cell will reduce the likelihood that the defective cell will prevent proper operation of the selected erase block.
摘要翻译：一种闪存阵列装置，具有可以单独擦除的多个擦除块。擦除块具有分离的源极线，其状态由源极线解码器控制。在阵列读取，编程和擦除操作中，未选择的擦除块的源线，未被读取，编程或擦除的块被设置为高阻抗级。如果一个取消选择的擦除块中的单元在某些方面是有缺陷的，使得单元导致漏电流，则与单元相关联的高阻抗源极线将降低有缺陷单元将阻止所选擦除块的正确操作的可能性。

59. 发明授权

US06496400B2 Memory architecture and addressing for optimized density in integrated circuit package or on circuit board 有权
标题翻译：存储器结构和寻址，用于集成电路封装或电路板上的优化密度
公开(公告)号：US06496400B2
公开(公告)日：2002-12-17
申请号：US09776447
申请日：2001-02-02
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C505
CPC分类号： G11C8/12 , G11C5/05
摘要： An electrically erasable and programmable read only memory (EEPROM) or other memory integrated circuit (IC) includes memory cells arranged in N blocks. The number of blocks, N, is selected to maximize utilization of the space available in a standard IC package. The number of blocks need not be an even power of two. More than log2(N) address bits are used to select between the blocks. A plurality of such memory ICs forms an array addressed by a memory controller, providing a number of directly addressable memory locations that need not be an even power of two. Addressing is provided for decoding chip select lines, block select lines, and other address lines. Staggered block decode lines associated with the memory blocks allow juxtaposition of the blocks to form a row in which connections are easily verified.
摘要翻译：电可擦除可编程只读存储器（EEPROM）或其他存储器集成电路（IC）包括以N个块排列的存储单元。选择块数N，以最大限度地利用标准IC封装中可用的空间。块的数量不需要是两个均匀的幂。大于log2（N）的地址位用于在块之间进行选择。多个这样的存储器IC形成由存储器控制器寻址的阵列，提供不需要是两个均匀功率的可直接寻址的存储器位置的数量。提供寻址用于解码芯片选择线，块选择线和其他地址线。与存储器块相关联的交错块解码线允许块的并置以形成容易验证连接的行。

60. 发明授权

US06324094B1 Apparatus for reading state of multistate non-volatile memory cells 有权
标题翻译：用于读取多态非易失性存储单元的状态的装置
公开(公告)号：US06324094B1
公开(公告)日：2001-11-27
申请号：US09560994
申请日：2000-04-28
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C702
CPC分类号： G11C5/147 , G11C7/06 , G11C7/14 , G11C8/00 , G11C11/5621 , G11C11/5642 , G11C16/08 , G11C16/28 , G11C2211/5634
摘要： An apparatus for determining the state of a multistate memory cell. The apparatus includes three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. The apparatus includes circuitry which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell.
摘要翻译：一种用于确定多状态存储器单元的状态的装置。该装置包括三个读出放大器，每个读出放大器具有相关联的参考单元，其产生用于输入到每个读出放大器的参考电压。该装置包括允许参考单元电流被改变以产生准确地确定阈值电压所需的参考电压或参考电压对，并因此产生编程或擦除的存储单元的状态所需的电路对。

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