专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20090164962A1 Method of Reducing Crosstalk Induced Noise in Circuitry Designs 有权
标题翻译：减少电路设计中串扰感应噪声的方法
公开(公告)号：US20090164962A1
公开(公告)日：2009-06-25
申请号：US11961440
申请日：2007-12-20
申请人： Sungjun Chun , Anand Haridass , Jesus Montanez , Xiaomin Shen
发明人： Sungjun Chun , Anand Haridass , Jesus Montanez , Xiaomin Shen
IPC分类号： G06F9/455
CPC分类号： G06F17/5036 , G06F17/5077
摘要： A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel to each other and have opposite directions. The method may identify all drivers and receivers in the physical circuit wiring design, and trace each interconnect line, starting with its driver, to determine a routed length from the driver to each segment break point of the interconnect line. The method may construct the spatial vector by defining an origin in the physical circuit wiring design. The method determines a starting point and an ending point of the spatial vector with respect to the origin. The starting point of the spatial vector is the break point of the interconnect wire segment closer to the driver. The ending point of the spatial vector is the break point of the interconnect wire segment farther from the driver. The method may define a Cartesian coordinate system with respect to the origin. The Cartesian coordinate system may be orthogonal with the interconnect wire segments of the physical circuit wiring design. The method may define one or more geometry windows in the physical circuit wiring design and compare the spatial vectors in each geometry window.
摘要翻译：在物理电路布线设计中减少串扰引起的噪声的方法在物理电路布线设计中为每个互连线段构造空间矢量。该方法比较了所述物理电路布线设计的空间矢量，并且识别彼此平行且具有相反方向的任何空间矢量。该方法可以识别物理电路布线设计中的所有驱动器和接收器，并且从其驱动器开始追踪每个互连线，以确定从驱动器到互连线的每个段断点的路由长度。该方法可以通过在物理电路布线设计中定义原点来构造空间矢量。该方法确定相对于原点的空间矢量的起始点和终点。空间矢量的起始点是互连线段靠近驾驶员的断点。空间矢量的终点是互连线段远离驾驶员的断点。该方法可以相对于原点定义笛卡尔坐标系。笛卡尔坐标系可以与物理电路布线设计的互连线段正交。该方法可以在物理电路布线设计中定义一个或多个几何窗口并比较每个几何窗口中的空间矢量。

52. 发明申请

US20090113107A1 DIFFERENTIAL TRANSMITTER CIRCUIT 失效
标题翻译：差分变送器电路
公开(公告)号：US20090113107A1
公开(公告)日：2009-04-30
申请号：US12350120
申请日：2009-01-07
申请人： Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
发明人： Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
IPC分类号： G06F13/40 , H04B3/00
CPC分类号： H04L25/0274 , H03F3/45197 , H03F2200/543 , H03F2203/45488
摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
摘要翻译：驱动器电路被配置为具有耦合到第一数据信号的一个输入和耦合到第二数据信号的第二输入的频率补偿差分放大器。差分放大器的每个级都用电流源偏置。驱动器电路产生耦合到第一传输线的输入的第一输出信号和耦合到第二传输线的输入的第二输出信号。第一和第二输出信号被产生为由补偿增益放大的第一和第二数据信号之间的差。相对于高频分量衰减输入信号的低频分量的补偿网络耦合在偏置差分放大器的电流源之间。第一和第二传输线的输出耦合到差分接收机的输入端，该差分接收机可以被频率补偿也可以不被频率补偿。

53. 发明申请

US20090048794A1 Method for Detecting Noise Events in Systems with Time Variable Operating Points 失效
标题翻译：用于检测具有时间可变工作点的系统中的噪声事件的方法
公开(公告)号：US20090048794A1
公开(公告)日：2009-02-19
申请号：US12262021
申请日：2008-10-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F19/00
CPC分类号： G06F1/305
摘要： A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
摘要翻译：提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。将经过时间平均的第一电压与第二电压进行比较。生成信号以指示处理器内的电路以启动动作以使电压进一步下降。

54. 发明授权

US07477068B2 System for reducing cross-talk induced source synchronous bus clock jitter 有权
标题翻译：减少串扰引起的源同步总线时钟抖动的系统
公开(公告)号：US07477068B2
公开(公告)日：2009-01-13
申请号：US12058689
申请日：2008-03-29
申请人： Bao G. Truong , Daniel Mark Dreps , Anand Haridass , John C. Schiff , Joel D. Ziegelbein
发明人： Bao G. Truong , Daniel Mark Dreps , Anand Haridass , John C. Schiff , Joel D. Ziegelbein
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译：使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以第一个时钟信号的补码。从第一时钟信号产生频率为F / 2的第二时钟信号。第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。在一个实施例中，使用延迟线电路来移位第二时钟。在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。

55. 发明申请

US20080252308A1 Power Grid Structure to Optimize Performance of a Multiple Core Processor 失效
标题翻译：电网结构优化多核处理器的性能
公开(公告)号：US20080252308A1
公开(公告)日：2008-10-16
申请号：US12143911
申请日：2008-06-23
申请人： Jean Audet , Louis B. Capps , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： Jean Audet , Louis B. Capps , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
IPC分类号： G01R31/26
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3296 , H01L23/50 , H01L2924/0002 , Y02D10/172 , H01L2924/00
摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
摘要翻译：减少数量的电压调节器模块为封装提供了减少的电源电压数量。该封装包括用于每个电压调节器模块的电压平面。管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。晶圆级测试确定优化每个核心或其他组件的性能的电压。给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。

56. 发明申请

US20080234955A1 Uniform Power Density Across Processor Cores at Burn-In 有权
标题翻译：老化处理器内核的均匀功率密度
公开(公告)号：US20080234955A1
公开(公告)日：2008-09-25
申请号：US12114032
申请日：2008-05-02
申请人： Louis Bennie Capps , Anand Haridass , Ronald Edward Newhart , Michael Jay Shapiro
发明人： Louis Bennie Capps , Anand Haridass , Ronald Edward Newhart , Michael Jay Shapiro
IPC分类号： G01R31/00 , G01R21/00
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译：提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。过程识别与多处理器相关联的多个处理器核心的功率管理数据集。该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。该过程在所选的一组处理器核心上启动老化测试。响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。

57. 发明授权

US07420378B2 Power grid structure to optimize performance of a multiple core processor 失效
标题翻译：电网结构优化多核处理器的性能
公开(公告)号：US07420378B2
公开(公告)日：2008-09-02
申请号：US11456658
申请日：2006-07-11
申请人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
发明人： Jean Audet , Louis B. Capps, Jr. , Glenn G. Daves , Anand Haridass , Ronald E. Newhart , Michael J. Shapiro
IPC分类号： G01R31/08 , G06F19/00
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3296 , H01L23/50 , H01L2924/0002 , Y02D10/172 , H01L2924/00
摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
摘要翻译：减少数量的电压调节器模块为封装提供了减少的电源电压数量。该封装包括用于每个电压调节器模块的电压平面。管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。晶圆级测试确定优化每个核心或其他组件的性能的电压。给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。

58. 发明授权

US07389195B2 Uniform power density across processor cores at burn-in 有权
标题翻译：老化时处理器内核的功率密度均匀
公开(公告)号：US07389195B2
公开(公告)日：2008-06-17
申请号：US11278303
申请日：2006-03-31
申请人： Louis Bennie Capps, Jr. , Anand Haridass , Ronald Edward Newhart , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Anand Haridass , Ronald Edward Newhart , Michael Jay Shapiro
IPC分类号： G01R31/00
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译：提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。过程识别与多处理器相关联的多个处理器核心的功率管理数据集。该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。该过程在所选的一组处理器核心上启动老化测试。响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。

59. 发明授权

US07382151B1 Method for reducing cross-talk induced source synchronous bus clock jitter 失效
标题翻译：减少串扰引起的源同步总线时钟抖动的方法
公开(公告)号：US07382151B1
公开(公告)日：2008-06-03
申请号：US11611200
申请日：2006-12-15
申请人： Bao G. Truong , Daniel Mark Dreps , Anand Haridass , John C. Schiff , Joel D. Ziegelbein
发明人： Bao G. Truong , Daniel Mark Dreps , Anand Haridass , John C. Schiff , Joel D. Ziegelbein
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译：使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以第一个时钟信号的补码。从第一时钟信号产生频率为F / 2的第二时钟信号。第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。在一个实施例中，使用延迟线电路来移位第二时钟。在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。

60. 发明申请

US20080087457A1 Ceramic Package in Which Far End Noise is Reduced Using Capacitive Cancellation by Offset Wiring 审中-公开
公开(公告)号：US20080087457A1
公开(公告)日：2008-04-17
申请号：US11951646
申请日：2007-12-06
申请人： Anand Haridass , Andreas Huber , Bao Truong , Roger Weekly
发明人： Anand Haridass , Andreas Huber , Bao Truong , Roger Weekly
IPC分类号： H05K7/06
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49163 , H01L2924/00
摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式