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1. 发明申请

US20080052542A1 System and Method to Optimize Multi-Core Microprocessor Performance Using Voltage Offsets 失效
标题翻译：使用电压偏移优化多核微处理器性能的系统和方法
公开(公告)号：US20080052542A1
公开(公告)日：2008-02-28
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译：提出了使用电压偏移来优化多核微处理器性能的系统和方法。多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。

2. 发明授权

US07721119B2 System and method to optimize multi-core microprocessor performance using voltage offsets 失效
标题翻译：使用电压补偿优化多核微处理器性能的系统和方法
公开(公告)号：US07721119B2
公开(公告)日：2010-05-18
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译：提出了使用电压偏移来优化多核微处理器性能的系统和方法。多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。

3. 发明申请

US20080234955A1 Uniform Power Density Across Processor Cores at Burn-In 有权
标题翻译：老化处理器内核的均匀功率密度
公开(公告)号：US20080234955A1
公开(公告)日：2008-09-25
申请号：US12114032
申请日：2008-05-02
申请人： Louis Bennie Capps , Anand Haridass , Ronald Edward Newhart , Michael Jay Shapiro
发明人： Louis Bennie Capps , Anand Haridass , Ronald Edward Newhart , Michael Jay Shapiro
IPC分类号： G01R31/00 , G01R21/00
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译：提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。过程识别与多处理器相关联的多个处理器核心的功率管理数据集。该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。该过程在所选的一组处理器核心上启动老化测试。响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。

4. 发明授权

US07389195B2 Uniform power density across processor cores at burn-in 有权
标题翻译：老化时处理器内核的功率密度均匀
公开(公告)号：US07389195B2
公开(公告)日：2008-06-17
申请号：US11278303
申请日：2006-03-31
申请人： Louis Bennie Capps, Jr. , Anand Haridass , Ronald Edward Newhart , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Anand Haridass , Ronald Edward Newhart , Michael Jay Shapiro
IPC分类号： G01R31/00
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译：提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。过程识别与多处理器相关联的多个处理器核心的功率管理数据集。该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。该过程在所选的一组处理器核心上启动老化测试。响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。

5. 发明授权

US07930129B2 Uniform power density across processor cores at burn-in 有权
标题翻译：老化时处理器内核的功率密度均匀
公开(公告)号：US07930129B2
公开(公告)日：2011-04-19
申请号：US12114032
申请日：2008-05-02
申请人： Louis Bennie Capps, Jr. , Anand Haridass , Ronald Edward Newhart , Michael J. Shapiro
发明人： Louis Bennie Capps, Jr. , Anand Haridass , Ronald Edward Newhart , Michael J. Shapiro
IPC分类号： G01R31/00 , G01R21/00
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译：提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。过程识别与多处理器相关联的多个处理器核心的功率管理数据集。该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。该过程在所选的一组处理器核心上启动老化测试。响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。

6. 发明申请

US20140025991A1 CORE DIAGNOSTICS AND REPAIR 有权
标题翻译：核心诊断和修复
公开(公告)号：US20140025991A1
公开(公告)日：2014-01-23
申请号：US13552237
申请日：2012-07-18
申请人： Sreekala Anandavally , Anand Haridass , Gerard M. Salem , Diyanesh B.C. Vidyapoornachary
发明人： Sreekala Anandavally , Anand Haridass , Gerard M. Salem , Diyanesh B.C. Vidyapoornachary
IPC分类号： G06F11/16
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/079 , G06F11/1428 , G06F11/16 , G06F11/2028 , G06F11/2041
摘要： Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.
摘要翻译：本公开的实施例涉及一种装置，其包括易受错误状况影响的第一核心，以及第二核心，被配置为对第一核心执行诊断以识别错误状况的原因以及纠正错误状况的动作命令恢复第一核心。

7. 发明授权

US08624297B2 Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density 有权
标题翻译：多层电路衬底制造和设计方法提供改进的传输线完整性和增加的路由密度
公开(公告)号：US08624297B2
公开(公告)日：2014-01-07
申请号：US12579517
申请日：2009-10-15
申请人： Sungjun Chun , Anand Haridass , Roger D. Weekly
发明人： Sungjun Chun , Anand Haridass , Roger D. Weekly
IPC分类号： H01L27/10 , H01L21/4763
CPC分类号： H01L21/76879 , H01L23/66 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H05K1/0253 , H05K1/112 , H05K3/4602 , H05K2201/09536 , H05K2201/09627 , H05K2201/0969 , H01L2224/0401
摘要： An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.
摘要翻译：集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级从信号承载PTH的顶部（或底部）到传输线参考平面。对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

8. 发明申请

US20130103927A1 CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS 有权
标题翻译：处理器链接的特征和验证
公开(公告)号：US20130103927A1
公开(公告)日：2013-04-25
申请号：US13281081
申请日：2011-10-25
申请人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F15/00 , G06F9/30
CPC分类号： G06F11/3089 , G01R31/31926 , G06F9/30 , G06F9/30007 , G06F11/22 , G06F11/221 , G06F11/3409 , G06F11/3414 , G06F11/349 , G06F15/00
摘要： A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.
摘要翻译：选择耦合第一处理器和第二处理器的处理器链接用于验证，并且识别与第一处理器和第二处理器相关联的多个通信参数设置。第一和第二处理器依次配置有每个通信参数设置。根据通信参数设置，从第一处理器向第二处理器提供一个或多个测试数据模式。至少部分地基于在第二处理器处接收到的测试数据模式来确定与所选择的处理器链路和通信参数设置相关联的性能测量。选择与最高性能测量值相关联的通信参数设置之一。所选择的通信参数设置被应用于第一和第二处理器，用于经由处理器链路在第一和第二处理器之间进行后续通信。

9. 发明授权

US07920978B2 Method for detecting noise events in systems with time variable operating points 失效
标题翻译：用于检测具有时间可变工作点的系统中的噪声事件的方法
公开(公告)号：US07920978B2
公开(公告)日：2011-04-05
申请号：US12262021
申请日：2008-10-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F1/26 , G06F11/30
CPC分类号： G06F1/305
摘要： A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
摘要翻译：提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。将经过时间平均的第一电压与第二电压进行比较。生成信号以指示处理器内的电路以启动动作以使电压进一步下降。

10. 发明授权

US07765504B2 Design method and system for minimizing blind via current loops 有权
标题翻译：通过电流回路最小化设计方法和系统
公开(公告)号：US07765504B2
公开(公告)日：2010-07-27
申请号：US11829179
申请日：2007-07-27
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Roger D. Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , H05K1/0216 , H05K1/115 , H05K3/0005 , H05K2201/09636
摘要： A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.
摘要翻译：用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进，而不需要广泛的电磁分析。检查通过携带关键信号的盲目附近的其他通孔是否适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。检查通过（s）的返回电流的距离，并且如果距离大于指定的阈值，则设计被调整以减小距离。如果盲目通过转换到外部层，合适的通孔将盲通孔内部的参考平面连接到外部端子。如果过渡在内层之间，合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。

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