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51. 发明授权

US5952050A Chemical dispensing system for semiconductor wafer processing 失效
标题翻译：化学分配系统用于半导体晶圆加工
公开(公告)号：US5952050A
公开(公告)日：1999-09-14
申请号：US944135
申请日：1997-10-06
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： B05D1/00 , B05D3/10 , H01L21/00 , B05D1/26 , B05D3/12
CPC分类号： H01L21/6715 , B05D1/005 , B05D3/107 , Y10S134/902 , Y10S438/906
摘要： A method for dispensing a chemical, such as an edge bead removal solvent, onto a semiconductor wafer comprising the steps of dispensing the chemical selectively onto the wafer and applying a suction to the area immediately surrounding the location at which the chemical is dispensed onto the wafer. Preferably, the suction is applied simultaneously with the dispensing of the chemical. One specific version of the invention provides an edge bead removal system wherein suction is applied to the area immediately surrounding the solvent dispensing nozzle to remove dissolved coating material and excess solvent from the wafer. In one aspect of this system, an apparatus for removing the edge bead includes a mechanism for dispensing a solvent selectively onto the edge of the wafer, and a mechanism surrounding the dispensing mechanism for vacuuming excess solvent and dissolved coating material from the edge of the wafer. The edge bead removal apparatus preferably also includes mechanisms for spinning the semiconductor wafer and coating material on the spinning wafer. Another aspect of the system provides a method for removing an edge bead of a coating of material that has been spun onto the surface of a semiconductor wafer. The method includes the steps of dispensing a solvent selectively onto the edge of the wafer to dissolve the coating material at the extreme edge of the wafer, and applying a suction to vacuum excess solvent and dissolved coating material from the wafer.
摘要翻译：一种用于将化学品（例如边缘珠去除溶剂）分配到半导体晶片上的方法，包括以下步骤：将化学品选择性地分配到晶片上并且将吸力施加到紧邻化学品被分配到晶片上的位置周围的区域。优选地，抽吸与化学品的分配同时施加。本发明的一个特定形式提供了边缘珠粒去除系统，其中将吸力施加到紧邻溶剂分配喷嘴的区域以从晶片去除溶解的涂层材料和多余的溶剂。在该系统的一个方面，用于去除边缘珠的装置包括用于将溶剂选择性地分配到晶片边缘的机构，以及围绕分配机构的机构，用于从晶片的边缘抽真空多余的溶剂和溶解的涂层材料。边缘珠去除装置优选地还包括用于在旋转晶片上旋转半导体晶片和涂层材料的机构。该系统的另一方面提供了一种用于去除已经旋转到半导体晶片的表面上的材料涂层的边缘珠的方法。该方法包括以下步骤：将溶剂选择性地分配到晶片的边缘上，以将涂层材料溶解在晶片的最外边缘，并且从晶片上抽吸过量的溶剂和溶解的涂料。

52. 发明授权

US5946595A Method of forming a local interconnect between electronic devices on a semiconductor substrate 失效
标题翻译：在半导体衬底上的电子器件之间形成局部互连的方法
公开(公告)号：US5946595A
公开(公告)日：1999-08-31
申请号：US818637
申请日：1997-03-14
申请人： Trung T. Doan , Zhiqiang Wu , Li Li
发明人： Trung T. Doan , Zhiqiang Wu , Li Li
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76895 , H01L21/28518
摘要： Disclosed is a method for forming a local interconnect with a self-aligned titanium silicide process on a semiconductor substrate. The initial step of the method is to form a thin titanium layer over the electronic devices to be provided with electrical communication. A polysilicon layer is then formed over the thin titanium layer, and in a further step, an implant mask is formed over portions of the polysilicon layer so as to pattern an area where the local interconnect is desired to be formed. Ions are then implanted into the polysilicon layer exposed by the implant mask, and the implant mask is then removed. In a further step, an etch process that etches either implanted or unimplanted polysilicon and is selective to the other is conducted. The remaining implanted polysilicon and titanium layers are then annealed to form titanium silicide, and the titanium that is not converted to titanium silicide is removed.
摘要翻译：公开了一种在半导体衬底上形成具有自对准钛硅化物工艺的局部互连的方法。该方法的初始步骤是在电子设备上形成薄钛层以提供电通信。然后在薄钛层上形成多晶硅层，并且在另一步骤中，在多晶硅层的部分上形成注入掩模，以便图案化需要形成局部互连的区域。然后将离子注入由植入掩模暴露的多晶硅层中，然后移除植入物掩模。在另一步骤中，进行蚀刻植入或未投影多晶硅并且对另一个选择性的蚀刻工艺。然后将剩余的注入的多晶硅和钛层退火以形成硅化钛，并且除去未转化为硅化钛的钛。

53. 发明授权

US5439551A Chemical-mechanical polishing techniques and methods of end point detection in chemical-mechanical polishing processes 失效
标题翻译：化学机械抛光技术和化学机械抛光工艺终点检测方法
公开(公告)号：US5439551A
公开(公告)日：1995-08-08
申请号：US205312
申请日：1994-03-02
申请人： Scott Meikle , Trung T. Doan
发明人： Scott Meikle , Trung T. Doan
IPC分类号： B24B37/04 , H01L21/304
CPC分类号： B24B37/013 , B24B37/042 , B24B49/003
摘要： A semiconductor processing method of detecting polishing end point in a chemical-mechanical polishing planarization process includes the following steps: a) chemical-mechanical polishing an outer surface of a semiconductor substrate using a chemical-mechanical polishing pad; b) during such chemical-mechanical polishing, measuring sound waves emanating from the chemical-mechanical polishing action of the substrate against the pad; c) detecting a change in the sound waves as the surface being chemical-mechanical polished becomes substantially planar; and d) ceasing chemical-mechanical polishing upon detection of the change. Alternately instead of ceasing chemical-mechanical polishing, a mechanical polishing process operational parameter could be changed upon detection of the change and then continuing mechanical polishing with the changed operational parameter. In another aspect of the invention, first and second layers to be polished are provided on a semiconductor wafer. The second layer is in situ measured during polishing to determine its substantial complete removal from the substrate by chemical-mechanical polishing. Such in situ measuring of the second layer during polishing might be conducted by a number of different manners, such as by acoustically, chemically, optically or others. Also claimed is a polishing apparatus for acoustically monitoring polishing action.
摘要翻译：在化学机械抛光平面化处理中检测抛光终点的半导体处理方法包括以下步骤：a）使用化学机械抛光垫对半导体衬底的外表面进行化学机械抛光; b）在这种化学机械抛光期间，测量从衬底的化学机械抛光作用发出的声波对衬垫; c）当化学机械抛光的表面变得基本平坦时，检测声波的变化; 和d）在检测到变化后停止化学机械抛光。或者替代停止化学机械抛光，可以在检测到变化后改变机械抛光工艺操作参数，然后用改变的操作参数继续机械抛光。在本发明的另一方面，将待抛光的第一和第二层设置在半导体晶片上。在抛光过程中原位测量第二层，以确定其通过化学机械抛光从基材中大量完全除去。在抛光期间原位测量第二层可以通过多种不同的方式进行，例如通过声学，化学，光学或其它方式进行。还要求的是用于声学监测抛光动作的抛光装置。

54. 发明授权

US5397908A Arrays of memory integrated circuitry 失效
标题翻译：存储器集成电路阵列
公开(公告)号：US5397908A
公开(公告)日：1995-03-14
申请号：US164896
申请日：1993-12-09
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/76 , H01L21/108 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L29/68 , H01L27/12
CPC分类号： H01L27/10852 , H01L21/76224 , H01L21/823481 , Y10S148/05
摘要： A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regions of moat volume into the substrate to define source/drain regions adjacent the field effect transistor gates. The invention also includes an array of memory integrated circuitry.
摘要翻译：半导体处理器件隔离方法包括：a）通过沟槽和再填充技术在衬底上提供非LOCOS绝缘器件隔离块，以在其间限定凹陷的沟槽体积; b）在护城河容积内提供栅极电介质; c）在衬底和栅极电介质上提供一层导电材料，其厚度足以完全填充相邻隔离块之间的护城河体积; d）化学机械抛光导电材料层以提供平坦化的上导电材料表面; e）对导电材料层进行光图案化和蚀刻，以提供覆盖在多个隔离块上的导电浇道，并且选择性地从导流槽体积的选定区域内去除导电材料，以在护城河体积内限定场效应晶体管栅极 ; 以及f）通过所选择的沟槽体积的区域提供导电性增强杂质到衬底中以限定与场效应晶体管栅极相邻的源极/漏极区域。本发明还包括一组存储器集成电路。

55. 发明授权

US5372973A Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology 失效
标题翻译：使用化学机械抛光技术在冷阴极发射器尖端周围形成自对准栅极结构的方法
公开(公告)号：US5372973A
公开(公告)日：1994-12-13
申请号：US53794
申请日：1993-04-27
申请人： Trung T. Doan , J. Brett Rolfson , Tyler A. Lowrey , David A. Cathey
发明人： Trung T. Doan , J. Brett Rolfson , Tyler A. Lowrey , David A. Cathey
IPC分类号： H01J1/304 , H01J9/02 , H01L21/3105 , H01L21/465
CPC分类号： H01J9/025 , H01L21/31053 , H01J2201/30426 , H01J2201/319 , H01J2209/0226
摘要： A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.
摘要翻译：用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii）化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料。

56. 发明授权

US5354490A Slurries for chemical mechanically polishing copper containing metal layers 失效
标题翻译：用于化学机械抛光含铜金属层的浆料
公开(公告)号：US5354490A
公开(公告)日：1994-10-11
申请号：US38460
申请日：1993-03-29
申请人： Chris C. Yu , Trung T. Doan
发明人： Chris C. Yu , Trung T. Doan
IPC分类号： H01L21/321 , C09K13/00
CPC分类号： H01L21/3212
摘要： A semiconductor processing method of chemical mechanical polishing a predominately copper containing metal layer on a semiconductor substrate includes, a) providing a chemical mechanical polishing slurry comprising H.sub.2 0, a solid abrasive material, and a third component selected from the group consisting of HNO.sub.3, H.sub.2 SO.sub.4, and AgNO.sub.3 or mixtures thereof; and b) chemical mechanical polishing a predominately copper containing metal layer on a semiconductor substrate with the slurry. Such slurry also constitutes part of the invention. Such slurry may also contain an additional oxidant selected from the group consisting of H.sub.2 0.sub.2, HOCl, KOCl, KMnO.sub.4 and CH.sub.3 COOH or mixtures thereof to form a copper oxide passivating-type layer at the copper surface.
摘要翻译：在半导体衬底上主要含铜的金属层进行化学机械抛光的半导体加工方法包括：a）提供包含H 2 O，固体研磨材料和选自HNO 3，H 2 SO 4的第三组分的化学机械抛光浆料，和AgNO 3或其混合物; 和b）在具有浆料的半导体衬底上化学机械抛光主要含铜的金属层。这种浆料也构成本发明的一部分。这种浆料还可含有选自H 2 O 2，HOCl，KOCl，KMnO 4和CH 3 COOH的其它氧化剂或其混合物，以在铜表面形成氧化铜钝化型层。

57. 发明授权

US5346587A Planarization of a gate electrode for improved gate patterning over non-planar active area isolation 失效
标题翻译：用于在非平面有源区隔离上改善栅极图案化的栅电极的平面化
公开(公告)号：US5346587A
公开(公告)日：1994-09-13
申请号：US105276
申请日：1993-08-12
申请人： Trung T. Doan , Charles H. Dennison
发明人： Trung T. Doan , Charles H. Dennison
IPC分类号： H01L21/28 , H01L21/768 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/7684
摘要： The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.
摘要翻译：本发明是一种在非平面起始衬底上提供平面化晶体管栅极的方法，通过沉积覆盖相邻场氧化物隔离区域的平坦化导电多晶硅材料层，使得导电多晶硅材料的高度延伸到场氧化物隔离区; 将导电硅化物材料层沉积在导电多晶硅材料上方并共同延伸; 然后对平坦化的导电多晶硅材料和导电硅化物材料进行构图，从而形成平坦化的晶体管栅极。

58. 发明授权

US5320880A Method of providing a silicon film having a roughened outer surface 失效
标题翻译：提供具有粗糙化外表面的硅膜的方法
公开(公告)号：US5320880A
公开(公告)日：1994-06-14
申请号：US155585
申请日：1993-11-18
申请人： Gurtej S. Sandhu , Trung T. Doan
发明人： Gurtej S. Sandhu , Trung T. Doan
IPC分类号： C23C16/24 , C23C16/505 , H01L21/02 , H01L21/205 , B05D3/06 , B05D3/02 , C23C16/00
CPC分类号： H01L28/84 , C23C16/24 , C23C16/505 , H01L21/02381 , H01L21/02532 , H01L21/0262
摘要： A method of providing a silicon film having a roughened outer surface atop a semiconductor wafer comprises: a) placing a semiconductor wafer into a plasma enhanced RF powered chemical vapor deposition reactor; and b) plasma enhanced chemical vapor depositing a layer of silicon over the wafer surface by providing quantities of a silicon source gas, a carrier gas, and TiCl.sub.4 to the reactor, the atomic ratio of the quantities of silicon source gas and TiCl.sub.4 being greater than or equal to 4 at the wafer surface; and by maintaining the reactor at a selected RF power, pressure and temperature; the RF power being supplied at a frequency of at least 5 MHz and preferably at least 10 MHz, the quantities of silicon source gas, RF power, temperature and pressure being effective to produce a predominately silicon film having an outer surface, the quantity of TiCl.sub.4 being effective to induce roughness into the outer silicon surface as compared to an outer silicon surface prepared under identical conditions but for introduction of TiCl.sub.4 but ineffective to produce a predominately titanium silicide film.
摘要翻译：提供在半导体晶片顶部具有粗糙化的外表面的硅膜的方法包括：a）将半导体晶片放置在等离子体增强的RF功率化学气相沉积反应器中; 和b）通过向反应器提供大量的硅源气体，载气和TiCl 4，等离子体增强化学气相沉积在晶片表面上的硅层，硅源气体和TiCl 4的量的原子比大于或在晶片表面等于4; 并通过将反应器维持在选定的RF功率，压力和温度; RF功率以至少5MHz，优选至少10MHz的频率提供，硅源气体的量，RF功率，温度和压力有效地产生主要具有外表面的硅膜，TiCl 4的量与在相同条件下制备的但用于引入TiCl 4但不能产生主要的硅化钛膜的外硅表面相比，有效地将粗糙度引入外硅表面。

59. 发明授权

US5278100A Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers 失效
标题翻译：用于在半导体晶片上沉积硅化钛的化学气相沉积技术
公开(公告)号：US5278100A
公开(公告)日：1994-01-11
申请号：US789585
申请日：1991-11-08
申请人： Trung T. Doan , Gurtej S. Sandhu
发明人： Trung T. Doan , Gurtej S. Sandhu
IPC分类号： H01L21/205 , H01L21/28 , H01L21/285 , H01L21/768 , H01L21/441
CPC分类号： H01L21/76855 , H01L21/285 , H01L21/28518 , H01L21/76843 , H01L21/76877 , Y10S148/147
摘要： A method of providing a conformal layer of TiSi.sub.x atop a semiconductor wafer within a chemical vapor deposition reactor includes the following steps: a) positioning a wafer within the reactor; b) injecting selected quantities of gaseous Ti(NR.sub.2).sub.4 precursor, gaseous silane and a carrier gas to within the reactor, where R is selected from the group consisting of H and a carbon containing radical, the quantities of Ti(NR.sub.2).sub.4 precursor and silane being provided in a volumetric ratio of Ti(NR.sub.2).sub.4 to silane of from 1:300 to 1:10, the quantity of carrier gas being from about 50 sccm to about 2000 sccm and comprising at least one noble gas; and c) maintaining the reactor at a selected pressure and a selected temperature which are effective for reacting the precursor and silane to deposit a film on the wafer, the film comprising a mixture of TiSi.sub.x and TiN, the selected temperature being from about 100.degree. C. to about 500.degree. C., and the selected pressure being from about 150 mTorr to about 100 Torr.
摘要翻译：在化学气相沉积反应器内提供半导体晶片顶部的TiSix共形层的方法包括以下步骤：a）将晶片定位在反应器内; b）将选定量的气态Ti（NR 2）4前体，气态硅烷和载气注入反应器内，其中R选自H和含碳基团，Ti（NR 2）4前体的量硅烷以Ti（NR 2）4与硅烷的体积比为1:300至1:10，载气量为约50sccm至约2000sccm并包含至少一种惰性气体; 以及c）将所述反应器保持在选择的压力和所选择的温度下，所述选择的温度对于使所述前体和硅烷反应以在所述晶片上沉积膜是有效的，所述膜包含TiSix和TiN的混合物，所述选定温度为约100℃ 至约500℃，并且所选择的压力为约150mTorr至约100Torr。

60. 发明授权

US5252518A Method for forming a mixed phase TiN/TiSi film for semiconductor manufacture using metal organometallic precursors and organic silane 失效
标题翻译：使用金属有机金属前体和有机硅烷形成用于半导体制造的混合TiN / TiSi膜的方法
公开(公告)号：US5252518A
公开(公告)日：1993-10-12
申请号：US845215
申请日：1992-03-03
申请人： Gurtej S. Sandhu , Trung T. Doan
发明人： Gurtej S. Sandhu , Trung T. Doan
IPC分类号： H01L21/285 , H01L21/768 , H01L23/532 , H01L21/441
CPC分类号： H01L23/53257 , H01L21/28518 , H01L21/76889 , H01L2924/0002 , Y10S148/147 , Y10S438/935
摘要： A LPCVD method for depositing a film of TiN on a semiconductor structure includes reacting an organometallic titanium source gas such as TMAT and organic silane as a reactive gas. The deposited film is a mixed phase of TiN and TiSi.sub.2 and is characterized by a low contact resistance, good step coverage and good barrier properties. The reaction is preferably carried out in a cold wall CVD reactor at relatively low temperatures (i.e. 200.degree. C.) and at pressures of from about 0.05 to 30 Torr.
摘要翻译：用于在半导体结构上沉积TiN膜的LPCVD方法包括使诸如TMAT的有机金属钛源气体和有机硅烷作为反应气体反应。沉积膜是TiN和TiSi2的混合相，其特征在于接触电阻低，阶梯覆盖率好，阻隔性好。该反应优选在相对低的温度（即200℃）和约0.05至30托的压力下在冷壁CVD反应器中进行。

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