专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20100140716A1 N/P METAL CRYSTAL ORIENTATION FOR HIGH-K METAL GATE Vt MODULATION 有权
标题翻译：用于高K金属门Vt调节的N / P金属晶体取向
公开(公告)号：US20100140716A1
公开(公告)日：2010-06-10
申请号：US12332057
申请日：2008-12-10
申请人： Simon Su-Horng Lin , Chi-Ming Yang , Chyi Shyuan Chern , Chin-Hsiang Lin
发明人： Simon Su-Horng Lin , Chi-Ming Yang , Chyi Shyuan Chern , Chin-Hsiang Lin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/28079 , H01L21/823842 , H01L27/0922 , H01L29/4958
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.
摘要翻译：本发明提供集成电路。集成电路包括具有第一区域和第二区域的半导体衬底; 在所述第一区域中的n型场效应晶体管（FET）的第一栅极堆叠; 以及第二区域中的p型FET的第二栅极堆叠。第一栅极堆叠包括在半导体衬底上的高k电介质层，在高k电介质层上具有第一取向的第一晶体金属层和第一晶体金属层上的导电材料层。第二栅极堆叠包括半导体衬底上的高k电介质层，在高k电介质层上具有第二取向的第二晶体金属层和第二晶体金属层上的导电材料层。

52. 发明授权

US09138861B2 CMP pad cleaning apparatus 有权
标题翻译： CMP垫清洁装置
公开(公告)号：US09138861B2
公开(公告)日：2015-09-22
申请号：US13396854
申请日：2012-02-15
申请人： Jiann Lih Wu , Bo-I Lee , Huang Soon Kang , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Jiann Lih Wu , Bo-I Lee , Huang Soon Kang , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： B24B53/00 , B24B53/017
CPC分类号： B24B53/017
摘要： The present disclosure relates to a two-phase cleaning element that enhances polishing pad cleaning so as to prevent wafer scratches and contamination in chemical mechanical polishing (CMP) processes. In some embodiments, the two-phase pad cleaning element comprises a first cleaning element and a second cleaning element configured to successively operate upon a section of a CMP polishing pad. The first cleaning element comprises a megasonic cleaning jet configured to utilize cavitation energy to dislodge particles embedded in the CMP polishing pad without damaging the surface of the polishing pad. The second cleaning element is configured to apply a high pressure mist, comprising two fluids, to remove by-products from the CMP polishing pad. By using megasonic cleaning to dislodge embedded particles a two-fluid mist to flush away by-products (e.g., including the dislodged embedded particles), the two-phase pad cleaning element enhances polishing pad cleaning.
摘要翻译：本公开内容涉及增强抛光垫清洁以防止晶片划伤和化学机械抛光（CMP）工艺中的污染的两相清洁元件。在一些实施例中，两相垫清洁元件包括第一清洁元件和第二清洁元件，其被配置为在CMP抛光垫的一部分上连续操作。第一清洁元件包括配置为利用空穴能量去除嵌入在CMP抛光垫中的颗粒而不损坏抛光垫的表面的兆声波清洗喷嘴。第二清洁元件构造成施加包括两种流体的高压雾以从CMP抛光垫移除副产物。通过使用兆声波清洗来移除嵌入式颗粒的双液雾以冲走副产物（例如，包括移出的嵌入颗粒），两相垫清洁元件增强了抛光垫清洁。

53. 发明授权

US09070534B2 Ion beam dimension control for ion implantation process and apparatus, and advanced process control 有权
标题翻译：离子束尺寸控制用于离子注入工艺和设备，以及先进的工艺控制
公开(公告)号：US09070534B2
公开(公告)日：2015-06-30
申请号：US13463942
申请日：2012-05-04
申请人： Chih-Hong Hwang , Chun-Lin Chang , Nai-Han Cheng , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Chih-Hong Hwang , Chun-Lin Chang , Nai-Han Cheng , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： H01J37/317 , H01J37/147 , H01J37/08 , H01J37/30 , H01L21/265 , H01L21/67 , H01J37/302 , H01L21/687
CPC分类号： H01J37/3171 , H01J37/1474 , H01J37/20 , H01J37/3023 , H01J37/3172 , H01J2237/12 , H01J2237/20228 , H01J2237/30477 , H01J2237/30483 , H01L21/265 , H01L21/68764
摘要： A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate.
摘要翻译：提供了用于离子注入方法和装置的过程控制方法，以在衬底上产生高剂量区域，例如可以补偿所指出的不均匀性。在离子注入工具中，分离的可控电极被设置为设置在离子束外部的多组相对的电极。光束阻挡器可以定位到离子束中。电极和光束阻挡器都是可控的，以减少入射到基板上的离子束的面积。电极和光束阻挡器也改变入射在表面上的减小面积的离子束的位置。衬底扫描通过离子束的速度可以在植入过程期间动态地改变，以在衬底中产生各种剂量浓度。

54. 发明授权

US09031684B2 Multi-factor advanced process control method and system for integrated circuit fabrication 有权
标题翻译：多因素先进的集成电路制造过程控制方法和系统
公开(公告)号：US09031684B2
公开(公告)日：2015-05-12
申请号：US13286337
申请日：2011-11-01
申请人： Nai-Han Cheng , Chin-Hsiang Lin , Chi-Ming Yang , Chun-Lin Chang , Chih-Hong Hwang
发明人： Nai-Han Cheng , Chin-Hsiang Lin , Chi-Ming Yang , Chun-Lin Chang , Chih-Hong Hwang
IPC分类号： G06F19/00 , G06F17/50 , H01L29/00 , H01L27/082 , H05K1/00
CPC分类号： G06F17/5063 , G06F2217/10
摘要： A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.
摘要翻译：公开了一种用于集成电路制造的方法和系统。在一个示例中，该方法包括确定晶片的第一工艺参数和晶片的第二工艺参数，对应于不同晶片特性的第一工艺参数和第二工艺参数; 基于所述第一处理参数和所述第二处理参数确定所述晶片的设备参数的变化; 基于确定的晶片的器件参数的变化，构造作为第一工艺参数和第二工艺参数的函数的器件参数的模型; 并基于该模型执行制造过程。

55. 发明授权

US08922122B2 Ion implantation with charge and direction control 有权
标题翻译：离子注入充电和方向控制
公开(公告)号：US08922122B2
公开(公告)日：2014-12-30
申请号：US13308614
申请日：2011-12-01
申请人： Chih-Hong Hwang , Chun-Lin Chang , Nai-Han Cheng , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Chih-Hong Hwang , Chun-Lin Chang , Nai-Han Cheng , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： H01J7/24
CPC分类号： H01J37/026 , H01J3/02 , H01J3/022 , H01J3/26 , H01J37/06 , H01J37/3171 , H01J2237/0041 , H01J2237/31705
摘要： The present disclosure provides for various advantageous methods and apparatus of controlling electron emission. One of the broader forms of the present disclosure involves an electron emission element, comprising an electron emitter including an electron emission region disposed between a gate electrode and a cathode electrode. An anode is disposed above the electron emission region, and a voltage set is disposed above the anode. A first voltage applied between the gate electrode and the cathode electrode controls a quantity of electrons generated from the electron emission region. A second voltage applied to the anode extracts generated electrons. A third voltage applied to the voltage set controls a direction of electrons extracted through the anode.
摘要翻译：本公开提供了控制电子发射的各种有利的方法和装置。本公开的更广泛形式之一涉及电子发射元件，其包括电子发射器，其包括设置在栅电极和阴极之间的电子发射区。阳极设置在电子发射区域的上方，并且在阳极上设置电压组。施加在栅电极和阴极之间的第一电压控制从电子发射区产生的电子量。施加到阳极的第二电压提取产生的电子。施加到电压组的第三电压控制通过阳极提取的电子的方向。

56. 发明授权

US08709528B2 Wafer processing method and system using multi-zone chuck 有权
标题翻译：晶圆加工方法和系统采用多区夹头
公开(公告)号：US08709528B2
公开(公告)日：2014-04-29
申请号：US13338885
申请日：2011-12-28
申请人： Nai-Han Cheng , Chi-Ming Yang , You-Hua Chou , Kuo-Sheng Chuang , Chin-Hsiang Lin
发明人： Nai-Han Cheng , Chi-Ming Yang , You-Hua Chou , Kuo-Sheng Chuang , Chin-Hsiang Lin
IPC分类号： C23C16/00
CPC分类号： H01L21/68785 , C23C14/50 , C23C14/54 , C23C16/4582 , C23C16/52 , H01L21/67098 , H01L21/67288 , H01L21/6831 , Y10T29/49998
摘要： In a wafer processing method and a wafer processing system, a first property on a back side of a wafer is measured. The back side of the wafer is supported on a multi-zone chuck having a plurality of zones with controllable clamping forces. The wafer is secured to the multi-zone chuck by controlling the clamping forces in the corresponding zones in accordance with measured values of the first property in the zones.
摘要翻译：在晶片处理方法和晶片处理系统中，测量晶片背面的第一特性。晶片的背面被支撑在具有可控夹紧力的多个区域的多区域卡盘上。通过根据区域中的第一属性的测量值控制相应区域中的夹紧力将晶片固定到多区域卡盘。

57. 发明授权

US08674451B2 N/P metal crystal orientation for high-K metal gate Vt modulation 有权
标题翻译： N / P金属晶体取向用于高K金属栅Vt调制
公开(公告)号：US08674451B2
公开(公告)日：2014-03-18
申请号：US12332057
申请日：2008-12-10
申请人： Simon Su-Horng Lin , Chi-Ming Yang , Chyi-Shyuan Chern , Chin-Hsiang Lin
发明人： Simon Su-Horng Lin , Chi-Ming Yang , Chyi-Shyuan Chern , Chin-Hsiang Lin
IPC分类号： H01L21/70
CPC分类号： H01L21/823857 , H01L21/28079 , H01L21/823842 , H01L27/0922 , H01L29/4958
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.
摘要翻译：本发明提供集成电路。集成电路包括具有第一区域和第二区域的半导体衬底; 在所述第一区域中的n型场效应晶体管（FET）的第一栅极堆叠; 以及第二区域中的p型FET的第二栅极堆叠。第一栅极堆叠包括在半导体衬底上的高k电介质层，在高k电介质层上具有第一取向的第一晶体金属层和第一晶体金属层上的导电材料层。第二栅极堆叠包括半导体衬底上的高k电介质层，在高k电介质层上具有第二取向的第二晶体金属层和第二晶体金属层上的导电材料层。

58. 发明授权

US08657963B2 In-situ backside cleaning of semiconductor substrate 有权
标题翻译：半导体衬底的原位背面清洗
公开(公告)号：US08657963B2
公开(公告)日：2014-02-25
申请号：US13240583
申请日：2011-09-22
申请人： Ming-Hsi Yeh , Kuo-Sheng Chuang , Ying-Hsueh Chang Chien , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Ming-Hsi Yeh , Kuo-Sheng Chuang , Ying-Hsueh Chang Chien , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： B08B1/00
CPC分类号： H01L21/67046 , H01L21/67051
摘要： The present disclosure provides a method and apparatus for cleaning a semiconductor wafer. In an embodiment of the method, a single wafer cleaning apparatus is provided and a wafer is positioned in the apparatus. A first chemical spray is dispensed onto a front surface of the wafer. A back surface of the wafer is cleaned while dispensing the first chemical spray. The cleaning of the back surface may include a brush and spray of cleaning fluids. An apparatus operable to clean the front surface and the back surface of a single semiconductor wafer is also described.
摘要翻译：本公开提供了一种用于清洁半导体晶片的方法和装置。在该方法的一个实施例中，提供单个晶片清洁装置，并且将晶片定位在装置中。将第一化学喷雾分配到晶片的前表面上。在分配第一化学喷雾的同时清洁晶片的背面。后表面的清洁可以包括刷子和喷射清洁流体。还描述了可操作以清洁单个半导体晶片的前表面和后表面的装置。

59. 发明授权

US08581204B2 Apparatus for monitoring ion implantation 有权
公开(公告)号：US08581204B2
公开(公告)日：2013-11-12
申请号：US13235088
申请日：2011-09-16
申请人： Chun-Lin Chang , Chih-Hong Hwang , Nai-Han Cheng , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Chun-Lin Chang , Chih-Hong Hwang , Nai-Han Cheng , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： G01T1/16
CPC分类号： H01L22/10 , H01J37/244 , H01J37/3171 , H01J2237/24542 , H01J2237/30455 , H01J2237/31703 , H01L21/265
摘要： An apparatus for monitoring an ion distribution of a wafer comprises a first sensor and a sensor. The first sensor, the second sensor and the wafer are placed in an effective range of a uniform ion implantation current profile. A controller determines the ion dose of each region of the wafer based upon the detected signal from the first sensor and the second sensor. In addition, the controller adjusts the scanning frequency of an ion beam or the movement speed of the wafer to achieve a uniform ion distribution on the wafer.

60. 发明申请

US20130210173A1 Multiple Zone Temperature Control for CMP 审中-公开
标题翻译：多区域温度控制CMP
公开(公告)号：US20130210173A1
公开(公告)日：2013-08-15
申请号：US13372872
申请日：2012-02-14
申请人： Jiann Lih Wu , Bo-I Lee , Soon Kang Huang , Chih-I Peng , Chi-Ming Yang , Chin-Hsiang Lin
发明人： Jiann Lih Wu , Bo-I Lee , Soon Kang Huang , Chih-I Peng , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： H01L21/66 , B24B49/00
CPC分类号： H01L22/12 , B24B37/013 , B24B37/015 , B24B49/105 , B24B49/14 , H01L22/26
摘要： To provide improved planarization, techniques in accordance with this disclosure include a CMP station that includes a plurality of concentric temperature control elements arranged over a number of concentric to-be-polished wafer surfaces. During polishing, a wafer surface planarity sensor monitors relative heights of the concentric to-be-polished wafer surfaces, and adjusts the temperatures of the concentric temperature control elements to provide an extremely well planarized wafer surface. Other systems and methods are also disclosed.
摘要翻译：为了提供改进的平面化，根据本公开的技术包括CMP站，其包括布置在多个同心待抛光晶片表面上的多个同心温度控制元件。在抛光期间，晶片表面平面度传感器监测同心待抛光的晶片表面的相对高度，并且调节同心温度控制元件的温度以提供非常好的平坦化晶片表面。还公开了其它系统和方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式