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51. 发明申请

US20080238632A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20080238632A1
公开(公告)日：2008-10-02
申请号：US12057671
申请日：2008-03-28
申请人： Takefumi ENDO , Takayuki Tsukamoto
发明人： Takefumi ENDO , Takayuki Tsukamoto
IPC分类号： H04B7/00
CPC分类号： H04B5/02 , H04B5/0031 , H04B5/0037
摘要： In an IC tag, when a semiconductor integrated circuit device is activated, an operation control unit sets existence/nonexistence of a communication distance limitation for reducing a communication distance to a state management unit. If the communication distance limitation is not set, a switch unit is turned ON and a demodulated command is inputted from a command demodulation circuit to a command decode unit. If the communication distance limitation is set, a power intensity monitor unit judges whether the power of a rectification circuit is a predetermined arbitrary field intensity or more. If the power is smaller than the predetermined arbitrary field intensity, the switch unit is turned OFF and various commands demodulated by the command demodulation circuit are not inputted to the command decode unit. As a result, the semiconductor integrated circuit device does not operate.
摘要翻译：在IC标签中，当半导体集成电路器件被激活时，操作控制单元设置存在/不存在通信距离限制，以减少与状态管理单元的通信距离。如果没有设定通信距离限制，则开关单元被接通，并且解调命令从命令解调电路输入到命令解码单元。如果设置了通信距离限制，则功率强度监视单元判定整流电路的功率是否为预定的任意场强度以上。如果功率小于预定的任意场强，则切换单元关闭，并且由命令解调电路解调的各种命令不被输入到命令解码单元。结果，半导体集成电路器件不工作。

52. 发明授权

US07245576B2 Optical recording medium and optical recording-reproducing method 失效
标题翻译：光记录介质和光记录再现方法
公开(公告)号：US07245576B2
公开(公告)日：2007-07-17
申请号：US10758481
申请日：2004-01-16
申请人： Katsutaro Ichihara , Sumio Ashida , Keiichiro Yusu , Kenji Todori , Takayuki Tsukamoto
发明人： Katsutaro Ichihara , Sumio Ashida , Keiichiro Yusu , Kenji Todori , Takayuki Tsukamoto
IPC分类号： G11B7/24
CPC分类号： B82Y10/00 , G11B7/00454 , G11B7/00456 , G11B7/005 , G11B7/242 , G11B7/243 , G11B7/253 , G11B7/257 , G11B7/261 , G11B7/268
摘要： An optical recording medium includes an optical recording layer, a separating layer formed on a reproducing light incident side of the optical recording layer, and a phase-change reproducing layer formed on the reproducing light incident side of the separating layer, absorbance of which phase-change reproducing layer is changed depending on whether a state of the optical recording layer is a recording mark or a space. A transfer portion to which a state of the optical recording layer is transferred is formed in a portion having high absorbance of the phase-change reproducing layer by irradiation with reproducing light, while a portion of the phase-change reproducing layer other than the transfer portion is kept in a state optically differing from the transfer portion.
摘要翻译：光记录介质包括光记录层，形成在光记录层的再现光入射侧的分离层和形成在分离层的再现光入射侧的相变再现层，改变再现层根据光学记录层的状态是记录标记还是空间而改变。通过照射再生光，在相变再生层的吸光度高的部分形成转印了光记录层的状态的转印部分，而转印部分以外的相变再生层的一部分保持在与转印部分光学不同的状态。

53. 发明申请

US20060077853A1 Apparatus and method for recording and reproducing hologram, and spatial light modulator therefor 失效
公开(公告)号：US20060077853A1
公开(公告)日：2006-04-13
申请号：US11209800
申请日：2005-08-24
申请人： Kazuki Matsumoto , Akiko Hirao , Rumiko Hayase , Takayuki Tsukamoto
发明人： Kazuki Matsumoto , Akiko Hirao , Rumiko Hayase , Takayuki Tsukamoto
IPC分类号： G11B7/00
CPC分类号： G11B7/128 , G11B7/0065 , G11B7/083
摘要： A hologram recording/reproducing apparatus includes a recording/reproducing optical system that guides at least one of an information beam and a reference beam to an optical recording medium; a spatial light modulator that is arranged in an optical path of the recording/reproducing optical system, and spatially modulates a beam guided via the recording/reproducing optical system to generate the information beam; a first misalignment detecting unit that detects a first misalignment between the recording/reproducing optical system and the spatial light modulator using a beam for detecting the first misalignment; and a first misalignment correcting unit that corrects the first misalignment based on the first misalignment detected by the first misalignment detecting unit.

54. 发明申请

US20060014081A1 Holographic recording medium and method of manufacturing the same 失效
公开(公告)号：US20060014081A1
公开(公告)日：2006-01-19
申请号：US11129403
申请日：2005-05-16
申请人： Rumiko Hayase , Akiko Hirao , Kazuki Matsumoto , Takayuki Tsukamoto , Katsutaro Ichihara , Urara Ichihara
发明人： Rumiko Hayase , Akiko Hirao , Kazuki Matsumoto , Takayuki Tsukamoto , Katsutaro Ichihara , Urara Ichihara
IPC分类号： G03H1/02 , G03C1/735
CPC分类号： G11B7/0065 , G03H2001/026 , G03H2001/0264 , G11B7/245 , G11B7/26
摘要： Disclosed is a holographic recording medium and methods of manufacturing the holographic recording medium. The example of the medium has a recording layer containing a three dimensionally cross-linked polymer matrix including an epoxy resin, a radically polymerizable monomer, and a photo radical polymerization initiator. The radically polymerizable monomer comprises both N-vinylcarbazole (VC) and N-vinylpyrrolidone (VP) or N-vinylcarbazole alone. The weight ratio of N-vinylcarbazole (VC) to the sum of N-vinylcarbazole (VC) and N-vinylpyrrolidone (VP), i.e., (VC/(VC+VP)), is not smaller than 0.75 and not larger than 1.0.

55. 发明授权

US09099180B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09099180B2
公开(公告)日：2015-08-04
申请号：US13599301
申请日：2012-08-30
申请人： Yoichi Minemura , Takayuki Tsukamoto , Takafumi Shimotori , Hiroshi Kanno , Tomonori Kurosawa , Mizuki Kaneko
发明人： Yoichi Minemura , Takayuki Tsukamoto , Takafumi Shimotori , Hiroshi Kanno , Tomonori Kurosawa , Mizuki Kaneko
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72
摘要： According to one embodiment, a semiconductor memory device includes a plurality of cell array blocks and a control circuit. The control circuit sets a selected bit line to have 0 volt, applies a first electric potential which is higher than 0 volt to a selected word line, applies a second electric potential which is higher than 0 volt and lower than the first electric potential to non-selected word lines other than the selected word line, applies a third electric potential which is 0 volt or more and lower than the second electric potential to a non-selected bit line adjacent to the selected bit line in an adjacent cell array block, applies the second electric potential to non-selected bit lines other than the non-selected bit line to which the third electric potential is applied, and changes a resistance status of the resistance variable film of the selected memory cell.
摘要翻译：根据一个实施例，半导体存储器件包括多个单元阵列块和控制电路。控制电路将所选择的位线设置为具有0伏特，对所选择的字线施加高于0伏的第一电位，将比第一电位高于0伏且低于第一电位的第二电位施加到非 - 除了所选字线以外的选定字线，将相邻单元阵列块中与选定位线相邻的未选位线施加0伏以上且低于第2电位的第3电位，对除了施加了第三电位的未选位线之外的非选择位线的第二电位，并且改变所选存储单元的电阻变化膜的电阻状态。

56. 发明授权

US08837199B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08837199B2
公开(公告)日：2014-09-16
申请号：US13599265
申请日：2012-08-30
申请人： Hiroshi Kanno , Yoichi Minemura , Mizuki Kaneko , Tomonori Kurosawa , Takafumi Shimotori , Takayuki Tsukamoto
发明人： Hiroshi Kanno , Yoichi Minemura , Mizuki Kaneko , Tomonori Kurosawa , Takafumi Shimotori , Takayuki Tsukamoto
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72
摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of memory cells, a plurality of wires, and a control circuit. The control circuit allows a first current to change a state to flow on a selected cell by applying a first potential difference between a pair of wires that sandwich the selected cell selected from the plurality of memory cells with respect to the semiconductor substrate vertically, and allows a second current lower than the first current to flow on an non-selected cell in the same direction as the direction of the first current by applying a second potential difference between a pair of wires that sandwich the non-selected cell connected to a wire shared with the selected cell on a different layer from the selected cell.
摘要翻译：根据一个实施例，半导体存储器件包括半导体衬底，多个存储单元，多根导线和控制电路。控制电路允许第一电流通过在相对于半导体衬底垂直地夹持从多个存储单元中选择的所选择的单元的一对导线之间施加第一电位差来改变选定单元上的状态，并允许低于第一电流的第二电流，在与所述第一电流的方向相同的方向上在未选择的单元上流动，通过在连接到共享的线的未选择的单元之间施加一对导线之间的第二电位差所选单元格与选定单元格不同的图层。

57. 发明授权

US08488367B2 Semiconductor memory device and method for controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08488367B2
公开(公告)日：2013-07-16
申请号：US13052174
申请日：2011-03-21
申请人： Takafumi Shimotori , Yoichi Minemura , Hiroshi Kanno , Takayuki Tsukamoto , Jun Nishimura , Masahiro Une
发明人： Takafumi Shimotori , Yoichi Minemura , Hiroshi Kanno , Takayuki Tsukamoto , Jun Nishimura , Masahiro Une
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/005 , G11C13/0064 , G11C13/0069 , G11C2213/72
摘要： According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again.
摘要翻译：根据一个实施例，一种用于控制半导体器件的方法包括确定一组存储器单元的选择位数，每个存储单元包括可变电阻元件，设置与选择位数对应的第一电压，将所设置的第一电压施加到存储单元组，并对已经施加了第一电压的存储单元组执行验证读取，并确定存储单元组是否通过验证读取。如果确定存储单元组不通过验证读取，则从选择位数中减去与传递的存储器单元相对应的位数，并且再次设置与减小的选择位数相对应的第一电压。

58. 发明授权

US08274815B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08274815B2
公开(公告)日：2012-09-25
申请号：US12886931
申请日：2010-09-21
申请人： Reika Ichihara , Takayuki Tsukamoto
发明人： Reika Ichihara , Takayuki Tsukamoto
IPC分类号： G11C11/00
CPC分类号： G11C11/00 , G11C2013/0083
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.
摘要翻译：根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。多个第二线延伸以与第一线相交。多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。控制电路被配置为控制施加到存储器单元的电压。控制电路在成形操作期间向可变电阻器施加第一脉冲电压。此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。

59. 发明申请

US20120134444A1 Semiconductor Device Having First and Second Demodulation Circuits for Wireless Communication 有权
标题翻译：具有用于无线通信的第一和第二解调电路的半导体器件
公开(公告)号：US20120134444A1
公开(公告)日：2012-05-31
申请号：US13298897
申请日：2011-11-17
申请人： Takayuki Tsukamoto
发明人： Takayuki Tsukamoto
IPC分类号： H03D1/24
CPC分类号： H04L27/06 , G06K7/0008 , H03D1/00 , H04B5/0031
摘要： A device receives ASK signals by using an ASK signal receiving circuit that is different from an ASK signal receiving circuit for R/W mode, when an NFC-enabled semiconductor device operates in a mode other than the R/W mode. An ASK signal receiving circuit for 100% ASK is provided on the side of a pair of transmitting terminals. This arrangement eliminates the influence of an ESD provided within an ASK signal receiving circuit for 10% ASK coupled to a pair of receiving terminals. There is no need for management of threshold values that are different according to type of ASK and it is possible to support different modulation schemes by a smaller circuit configuration.
摘要翻译：当NFC功能半导体器件以除R / W模式之外的模式工作时，器件通过使用与用于R / W模式的ASK信号接收电路不同的ASK信号接收电路来接收ASK信号。在一对发送端子的一侧设置有用于100％ASK的ASK信号接收电路。这种布置消除了在与一对接收终端耦合的10％ASK的ASK信号接收电路内提供的ESD的影响。不需要根据ASK的类型来管理不同的阈值，并且可以通过较小的电路配置来支持不同的调制方案。

60. 发明申请

US20110235400A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110235400A1
公开(公告)日：2011-09-29
申请号：US13052174
申请日：2011-03-21
申请人： Takafumi Shimotori , Yoichi Minemura , Hiroshi Kanno , Takayuki Tsukamoto , Jun Nishimura , Masahiro Une
发明人： Takafumi Shimotori , Yoichi Minemura , Hiroshi Kanno , Takayuki Tsukamoto , Jun Nishimura , Masahiro Une
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/005 , G11C13/0064 , G11C13/0069 , G11C2213/72
摘要： According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again.
摘要翻译：根据一个实施例，一种用于控制半导体器件的方法包括确定一组存储器单元的选择位数，每个存储单元包括可变电阻元件，设置与选择位数对应的第一电压，将所设置的第一电压施加到存储单元组，并对已经施加了第一电压的存储单元组执行验证读取，并确定存储单元组是否通过验证读取。如果确定存储单元组不通过验证读取，则从选择位数中减去与传递的存储器单元相对应的位数，并且再次设置与减小的选择位数相对应的第一电压。

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