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51. 发明授权

US5312778A Method for plasma processing using magnetically enhanced plasma chemical vapor deposition 失效
标题翻译：使用磁增强等离子体化学气相沉积的等离子体处理方法
公开(公告)号：US5312778A
公开(公告)日：1994-05-17
申请号：US618142
申请日：1990-11-23
申请人： Kenneth S. Collins , Chan-Lon Yang , John M. White
发明人： Kenneth S. Collins , Chan-Lon Yang , John M. White
IPC分类号： C23C14/35 , C23C14/40 , C23C16/50 , C23C16/509 , C23F4/00 , H01J37/32 , H01L21/302 , H01L21/3065 , H05H1/46 , H01L21/00 , H01L21/02 , H01L21/463
CPC分类号： H01J37/32082 , C23C16/509 , H01J37/32091 , H01J37/32174 , H01J37/32623 , H05H1/46
摘要： A method for plasma processing characterized by the steps of disposing a wafer proximate to a cathode within a process chamber, releasing a gas into the chamber, applying R.F. power in the VHF/UHF frequency range to the cathode to form a plasma within the chamber, developing a magnetic field within the chamber having flux lines substantially perpendicular to the surface of the wafer, and varying the strength of the magnetic field until a desired cathode sheath voltage is attained. The apparatus includes a chamber, a wafer-supporting cathode disposed within the chamber, a mechanism for introducing gas into the chamber, an R.F. power source coupled to the cathode operating in the frequency from about 50-800 megahertz, an electromagnetic coil disposed around the chamber adapted to develop a magnetic field within the chamber which is substantially perpendicular to the wafer and a variable output power supply coupled to the coil to vary the magnetic field strength and therefore the cathode sheath voltage within the chamber.
摘要翻译：一种用于等离子体处理的方法，其特征在于以下步骤：在处理室内设置靠近阴极的晶片，将气体释放到室中，施加R.F. 在VHF / UHF频率范围内的功率到阴极以在室内形成等离子体，在室内形成具有基本上垂直于晶片表面的磁通线的磁场，并且改变磁场的强度，直到所需的阴极获得鞘电压。该装置包括腔室，设置在腔室内的晶片支撑阴极，用于将气体引入腔室的机构，R.F. 电源，其耦合到以大约50-800兆赫的频率工作的阴极;设置在所述腔室周围的电磁线圈，其适于在所述腔室内开发基本上垂直于所述晶片的磁场;以及耦合到所述线圈的可变输出电源以改变室内的磁场强度和因此的阴极护套电压。

52. 发明授权

US5300460A UHF/VHF plasma for use in forming integrated circuit structures on semiconductor wafers 失效
标题翻译： UHF / VHF等离子体，用于在半导体晶片上形成集成电路结构
公开(公告)号：US5300460A
公开(公告)日：1994-04-05
申请号：US32744
申请日：1993-03-16
申请人： Kenneth S. Collins , Craig A. Roderick , Chan-Lon Yang , David N. K. Wang , Dan Maydan
发明人： Kenneth S. Collins , Craig A. Roderick , Chan-Lon Yang , David N. K. Wang , Dan Maydan
IPC分类号： C23C16/509 , H01J37/32 , H05H1/46 , H01L21/00 , H01L21/02 , H01L21/22 , H01L21/265
CPC分类号： H01J37/32174 , C23C16/509 , H01J37/32082 , H05H1/46
摘要： An improved method of fabricating integrated circuit structures on semiconductor wafers using a plasma-assisted process is disclosed wherein the plasma is generated by a VHF/UHF power source at a frequency ranging from about 50 to about 800 MHz. Low pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out within a pressure range not exceeding about 500 milliTorr; with a ratio of anode to cathode area of from about 2:1 to about 20:1, and an electrode spacing of from about 5 cm. to about 30 cm. High pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out with a pressure ranging from over 500 milliTorr up to 50 Torr or higher; with an anode to cathode electrode spacing of less than about 5 cm. By carrying out plasma-assisted processes using plasma operated within a range of from about 50 to about 800 MHz, the electrode sheath voltages are maintained sufficiently low, so as to avoid damage to structures on the wafer, yet sufficiently high to preferably permit initiation of the processes without the need for supplemental power sources. Operating in this frequency range may also result in reduction or elimination of microloading effects.
摘要翻译：公开了使用等离子体辅助方法制造半导体晶片上的集成电路结构的改进方法，其中等离子体由VHF / UHF电源以约50至约800MHz的频率产生。低压等离子体辅助蚀刻或沉积工艺，即工艺可以在不超过约500毫托的压力范围内进行; 阳极与阴极面积的比例为约2:1至约20:1，电极间距约为5cm。到约30厘米。高压等离子体辅助蚀刻或沉积工艺，即工艺可以在500毫乇至50乇以上的压力下进行; 阳极至阴极间距小于约5厘米。通过使用在约50至约800MHz的范围内操作的等离子体等离子体辅助处理，电极护套电压保持足够低，以避免损坏晶片上的结构，但足够高以优选允许引发该过程无需补充电源。在该频率范围内工作也可能导致微载物效应的降低或消除。

53. 发明授权

US08404591B2 Method of fabricating complementary metal-oxide-semiconductor (CMOS) device 有权
标题翻译：互补金属氧化物半导体（CMOS）器件的制造方法
公开(公告)号：US08404591B2
公开(公告)日：2013-03-26
申请号：US13482044
申请日：2012-05-29
申请人： Chiu-Hsien Yeh , Chan-Lon Yang , Chin-Cheng Chien , Lien-Fa Hung , Yun-Cheng Kao
发明人： Chiu-Hsien Yeh , Chan-Lon Yang , Chin-Cheng Chien , Lien-Fa Hung , Yun-Cheng Kao
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L29/517 , H01L21/31111 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L29/4966 , H01L29/513
摘要： A method of fabricating a MOS device comprises steps as follows: An interfacial layer, a high-k dielectric layer and a cover layer on a substrate are sequentially formed. Then an in-situ wet etching step is performed by sequentially using a first etching solution to etch the cover layer and using a second etching solution to etch the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution.
摘要翻译：制造MOS器件的方法包括以下步骤：依次形成界面层，高k电介质层和衬底上的覆盖层。然后，通过依次使用第一蚀刻溶液蚀刻覆盖层并使用第二蚀刻溶液来蚀刻高k电介质层和界面层直到基板被暴露来进行原位湿蚀刻步骤，其中第二蚀刻溶液是含有第一蚀刻溶液的混合蚀刻溶液。

54. 发明申请

US20130001707A1 FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF 审中-公开
标题翻译： MOS晶体管的制造方法，Fin场效应晶体管及其制造方法
公开(公告)号：US20130001707A1
公开(公告)日：2013-01-03
申请号：US13174711
申请日：2011-06-30
申请人： Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang , Chan-Lon Yang , Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang , Chan-Lon Yang , Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L21/02332 , H01L29/512 , H01L29/66795 , H01L29/785
摘要： A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.
摘要翻译： MOS晶体管的制造方法包括以下步骤。提供基板。在基板上形成栅介电层。进行包含氮等离子体和氦气的氮化处理，以对栅介质层进行氮化。还提供了鳍状场效应晶体管及其制造方法。

55. 发明授权

US08298950B2 Method of etching sacrificial layer 有权
标题翻译：蚀刻牺牲层的方法
公开(公告)号：US08298950B2
公开(公告)日：2012-10-30
申请号：US12830370
申请日：2010-07-05
申请人： Chan-Lon Yang , Yeng-Peng Wang , Chiu-Hsien Yeh
发明人： Chan-Lon Yang , Yeng-Peng Wang , Chiu-Hsien Yeh
IPC分类号： H01L21/311
CPC分类号： H01L21/823842 , H01L21/32134 , H01L21/32135 , H01L27/11 , H01L27/1104
摘要： An exemplary method of etching sacrificial layer includes steps of: providing a substrate formed with a sacrificial layer and defined with a first region and a second region, the sacrificial layer disposed in both the first and second regions; forming a hard mask covering the first region while exposing the second region; performing a first etching process on the sacrificial layer to thin the sacrificial layer while forming a byproduct film overlying the thinned sacrificial layer; performing a second etching process on the byproduct film to remove a portion of the byproduct layer for exposing a portion of the thinned sacrificial layer, while another portion of the byproduct film disposed on sidewalls of the thinned sacrificial layer being remained; and performing a third etching process on the thinned sacrificial layer, to remove the portion of the thinned sacrificial layer exposed in the second etching process.
摘要翻译：蚀刻牺牲层的示例性方法包括以下步骤：提供形成有牺牲层并且由第一区域和第二区域限定的衬底，所述牺牲层设置在第一和第二区域中; 在暴露所述第二区域的同时形成覆盖所述第一区域的硬掩模; 在所述牺牲层上执行第一蚀刻工艺以使所述牺牲层变薄，同时形成覆盖所述薄化的牺牲层的副产物膜; 在副产品膜上执行第二蚀刻工艺以去除副产物层的一部分，用于暴露部分减薄的牺牲层，同时保留设置在减薄的牺牲层的侧壁上的副产物膜的另一部分; 以及对所述减薄的牺牲层执行第三蚀刻工艺，以去除在所述第二蚀刻工艺中暴露的所述薄化牺牲层的所述部分。

56. 发明申请

US20120193796A1 POLYSILICON LAYER AND METHOD OF FORMING THE SAME 有权
标题翻译：多晶硅层及其形成方法
公开(公告)号：US20120193796A1
公开(公告)日：2012-08-02
申请号：US13018009
申请日：2011-01-31
申请人： Chien-Liang Lin , Yun-Ren Wang , Ying-Wei Yen , Wen-Yi Teng , Chan-Lon Yang
发明人： Chien-Liang Lin , Yun-Ren Wang , Ying-Wei Yen , Wen-Yi Teng , Chan-Lon Yang
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L29/4916 , H01L21/26506 , H01L21/26513 , H01L21/28035 , H01L29/4925
摘要： The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
摘要翻译：提供了形成多晶硅层的方法。在基板上形成具有第一粒径的第一多晶硅层。在第一多晶硅层上形成第二晶粒尺寸的第二多晶硅层。第一粒度小于第二粒度。具有较小晶粒尺寸的第一多晶硅层可用作随后沉积的基底，使得其上形成的第二多晶硅层具有更平坦的形貌，因此表面粗糙度降低，并且晶片内的Rs均匀性得到改善。

57. 发明授权

US07772064B2 Method of fabricating self-aligned contact 有权
标题翻译：自对准接触的方法
公开(公告)号：US07772064B2
公开(公告)日：2010-08-10
申请号：US11681993
申请日：2007-03-05
申请人： Chan-Lon Yang
发明人： Chan-Lon Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76804 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region thereon. Next, a lower opening corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper opening self-aligned to and communicated with the lower opening is formed in the second dielectric layer, wherein the upper opening and the lower opening constitute a self-aligned contact opening. Afterwards, the self-aligned contact opening is filled with a conductive layer.
摘要翻译：提供一种制造自对准接触的方法。在其上具有接触区域的基板上形成第一介电层。接下来，在第一电介质层中形成对应于接触区域的下开口。此后，在第一电介质层上形成第二电介质层，然后在第二电介质层中形成自对准并与下开口连通的上开口，其中上开口和下开口构成自对准接触开口之后，自对准的接触开口填充有导电层。

58. 发明授权

US07253094B1 Methods for cleaning contact openings to reduce contact resistance 有权
标题翻译：清洁接触开口以减少接触电阻的方法
公开(公告)号：US07253094B1
公开(公告)日：2007-08-07
申请号：US10993031
申请日：2004-11-19
申请人： Jie Zhang , Vinay Krishna , Chan-Lon Yang
发明人： Jie Zhang , Vinay Krishna , Chan-Lon Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/02063 , H01L21/32134 , H01L21/76814
摘要： A method for processing a semiconductor topography which includes removing metal oxide layers from the bottom of contact openings is provided. In some embodiments, the method may include etching openings within a dielectric layer to expose conductive and silicon surfaces within the semiconductor topography is provided. In such cases, the method further includes exposing the semiconductor topography to an etch process adapted to remove metal oxide material from the conductive surfaces without substantially removing material from the silicon surfaces. In some cases, the etch chemistry used for the etch process may include sulfuric acid. In addition or alternatively, the etch chemistry may include hydrogen peroxide. In any case, the etch chemistry may be distinct from chemistries used to remove residual matter generated from the etch process used to form the openings within the dielectric and/or the removal of the masking layer used to pattern the openings.
摘要翻译：提供一种处理半导体形貌的方法，其包括从接触孔的底部去除金属氧化物层。在一些实施例中，该方法可以包括蚀刻介电层内的开口以暴露半导体形貌中的导电和硅表面。在这种情况下，该方法还包括将半导体形貌暴露于适于从导电表面除去金属氧化物材料的蚀刻工艺，而基本上不从硅表面去除材料。在一些情况下，用于蚀刻工艺的蚀刻化学可能包括硫酸。另外或替代地，蚀刻化学品可以包括过氧化氢。在任何情况下，蚀刻化学可能不同于用于去除由用于在电介质中形成开口的蚀刻工艺产生的残余物质和/或去除用于图案化开口的掩模层的化学物质。

59. 发明授权

US06545420B1 Plasma reactor using inductive RF coupling, and processes 失效
标题翻译：使用感应式RF耦合的等离子体反应器和工艺
公开(公告)号：US06545420B1
公开(公告)日：2003-04-08
申请号：US08468573
申请日：1995-06-06
申请人： Kenneth S. Collins , Craig A. Roderick , John R. Trow , Chan-Lon Yang , Jerry Yuen-Kui Wong , Jeffrey Marks , Peter R. Keswick , David W. Groechel , Jay D. Pinson, II , Tetsuya Ishikawa , Lawrence Chang-Lai Lei , Masato M. Toshima
发明人： Kenneth S. Collins , Craig A. Roderick , John R. Trow , Chan-Lon Yang , Jerry Yuen-Kui Wong , Jeffrey Marks , Peter R. Keswick , David W. Groechel , Jay D. Pinson, II , Tetsuya Ishikawa , Lawrence Chang-Lai Lei , Masato M. Toshima
IPC分类号： H01J724
CPC分类号： H01J37/32871 , C23C16/509 , C23C16/517 , H01F2029/143 , H01J37/32082 , H01J37/32091 , H01J37/321 , H01J37/3211 , H01J37/32146 , H01J37/32165 , H01J37/32174 , H01J37/3222 , H01J37/32293 , H01J37/32458 , H01J37/32522 , H01J37/3266 , H01J37/32688 , H01J37/32706 , H01L21/31116 , H01L21/6831
摘要： A domed plasma reactor chamber uses an antenna driven by RF energy (LF, MF, or VHF) which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching metals, dielectrics and semiconductor materials. Auxiliary RF bias energy applied to the wafer support cathode controls the cathode sheath voltage and controls the ion energy independent of density. Various magnetic and voltage processing enhancement techniques are disclosed, along with etch processes, deposition processes and combined etch/deposition processed. The disclosed invention provides processing of sensitive devices without damage and without microloading, thus providing increased yields.
摘要翻译：圆顶等离子体反应室使用由RF能量（LF，MF或VHF）驱动的天线，其被感应耦合在反应器穹顶内。天线在室内产生高密度，低能量等离子体，用于蚀刻金属，电介质和半导体材料。施加到晶片支撑阴极的辅助RF偏置能量控制阴极护套电压并且独立于密度来控制离子能量。公开了各种磁和电压处理增强技术，连同蚀刻工艺，沉积工艺和组合蚀刻/沉积处理。所公开的发明提供敏感设备的处理而不损坏和不加载，从而提高产量。

60. 发明授权

US06492250B1 Polycide gate structure and method of manufacture 失效
标题翻译：聚酰胺门结构及其制造方法
公开(公告)号：US06492250B1
公开(公告)日：2002-12-10
申请号：US09638923
申请日：2000-08-15
申请人： Hidetake Horiuch , Chan-Lon Yang
发明人： Hidetake Horiuch , Chan-Lon Yang
IPC分类号： H01L214763
CPC分类号： H01L29/4933 , H01L21/28061
摘要： A polycide gate structure and a method of forming the polycide gate. A substrate having a gate dielectric layer, a polysilicon layer, a silicide layer and an insulation layer thereon is provided. The polysilicon layer is above the gate dielectric layer, the silicide layer is above the polysilicon layer, and the insulation layer is above the silicide layer. A patterned photoresist layer is formed over the insulation layer. Using the photoresist layer as a mask, an anisotropic etching operation is carried out to remove the exposed insulation layer. Again using the photoresist layer as a mask, a first type of plasma is used to carry out a first anisotropic etching operation to remove the exposed silicide layer. A metallic oxide layer is formed on the sidewalls of the silicide layer by the oxidation of a portion of the retained silicide layer. Using the photoresist layer as a mask, a second type of plasma is used to carry out a second anisotropic etching operation to remove the exposed polysilicon layer. The metallic oxide layer is resistant to attack by the second type of plasma.
摘要翻译：多晶硅栅极结构和形成多晶硅栅极的方法。提供了具有栅极电介质层，多晶硅层，硅化物层及其绝缘层的衬底。多晶硅层位于栅极电介质层之上，硅化物层位于多晶硅层上方，绝缘层位于硅化物层之上。在绝缘层上形成图案化的光致抗蚀剂层。使用光致抗蚀剂层作为掩模，进行各向异性蚀刻操作以去除暴露的绝缘层。再次使用光致抗蚀剂层作为掩模，使用第一类型的等离子体进行第一各向异性蚀刻操作以除去暴露的硅化物层。通过一部分保留的硅化物层的氧化，在硅化物层的侧壁上形成金属氧化物层。使用光致抗蚀剂层作为掩模，使用第二类型的等离子体进行第二种各向异性蚀刻操作以去除暴露的多晶硅层。金属氧化物层耐受第二类型等离子体的侵蚀。

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