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51. 发明申请

US20120159184A1 Technique for Supporting Multiple Secure Enclaves 有权
标题翻译：支持多个安全漏洞的技术
公开(公告)号：US20120159184A1
公开(公告)日：2012-06-21
申请号：US12972406
申请日：2010-12-17
申请人： Simon P. Johnson , Uday R. Savagaonkar , Vincent R. Scarlata , Francis X. McKeen , Carlos V. Rozas
发明人： Simon P. Johnson , Uday R. Savagaonkar , Vincent R. Scarlata , Francis X. McKeen , Carlos V. Rozas
IPC分类号： G06F21/00
CPC分类号： G06F12/1466 , G06F21/53 , G06F21/6218 , G06F21/64 , G06F21/645
摘要： A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
摘要翻译：一种在计算机系统内实现安全应用和数据完整性的技术。在一个实施例中，建立一个或多个安全空间，其中可以存储和执行应用和数据。

52. 发明申请

US20090089564A1 Protecting a Branch Instruction from Side Channel Vulnerabilities 审中-公开
标题翻译：保护分支指令免受副渠道漏洞的影响
公开(公告)号：US20090089564A1
公开(公告)日：2009-04-02
申请号：US11951999
申请日：2007-12-06
申请人： Ernie F. Brickell , Sergiu Ghetie , Shay Gueron , Adil Karrar , Francis X. McKeen
发明人： Ernie F. Brickell , Sergiu Ghetie , Shay Gueron , Adil Karrar , Francis X. McKeen
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30003 , G06F9/30076 , G06F9/30181 , G06F9/30185 , G06F9/3842 , G06F9/3846 , G06F21/556
摘要： Embodiments of an invention to protection a branch instruction from side channel vulnerabilities are described. In one embodiment, a method includes receiving a request to modify the operation of a processor to protect against side channel attacks, and modifying branch prediction operation in response to the request.
摘要翻译：描述了保护分支指令免受侧面通道漏洞的发明的实施例。在一个实施例中，一种方法包括接收修改处理器的操作以防止侧信道攻击的请求，以及响应于该请求修改分支预测操作。

53. 发明授权

US06981129B1 Breaking replay dependency loops in a processor using a rescheduled replay queue 失效
标题翻译：使用重新安排的重播队列在处理器中重新播放依赖循环
公开(公告)号：US06981129B1
公开(公告)日：2005-12-27
申请号：US09705668
申请日：2000-11-02
申请人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
发明人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译：使用重新安排的重播队列在处理器中重新播放依赖循环。所述处理器包括用于接收多个指令的重放队列，以及执行所述多个指令的执行单元。调度器耦合在重播队列和执行单元之间。调度器推测性地调度用于执行的指令，并且为多个指令中的每一个递增计数器，以反映多个指令中的每一个已被执行的次数。当计数器不超过最大重放次数时，或者当计数器超过最大重放次数时，当指令执行安全时，调度器也将每条指令分派给执行单元。检查器耦合到执行单元以确定每个指令是否已成功执行。检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

54. 发明授权

US6154828A Method and apparatus for employing a cycle bit parallel executing instructions 失效
标题翻译：用于使用循环位指示并行执行指令的执行完成的方法和装置
公开(公告)号：US6154828A
公开(公告)日：2000-11-28
申请号：US072632
申请日：1993-06-03
申请人： Joseph Dominic Macri , Francis X. McKeen , Joel S. Emer , William Robert Grundmann , Robert P. Nix , David Arthur James Webb, Jr.
发明人： Joseph Dominic Macri , Francis X. McKeen , Joel S. Emer , William Robert Grundmann , Robert P. Nix , David Arthur James Webb, Jr.
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838
摘要： A method and apparatus including means for storing an executable file which includes a group of bits which define functional operations and cycle bits associated with each functional operation and means for completing a variable number of the functional operations in parallel during a single execution cycle in accordance with a state of the associated cycle bit. The method and apparatus eliminates the need for complex data dependency checking hardware and allows a minimum amount of control logic to complete execution of executable files. The method and apparatus further minimizes the necessity of adding null operations (NOPs) to executable files which reduces the amount of storage space necessary to store the executable files and allows executable files to be used on multiple hardware implementations and for register values to be used for multiple purposes during single execution cycles.
摘要翻译：一种方法和装置，包括用于存储可执行文件的装置，该可执行文件包括定义与每个功能操作相关联的功能操作和周期位的一组比特，以及用于在单个执行周期期间根据单个执行周期并行地完成可变数量的功能操作的装置相关联的周期位的状态。该方法和装置消除了对复杂数据依赖性检查硬件的需要，并允许最小量的控制逻辑来完成可执行文件的执行。该方法和装置进一步最小化了对可执行文件添加空操作（NOP）的必要性，这减少了存储可执行文件所需的存储空间量，并允许在多个硬件实现上使用可执行文件，并且使用用于在单个执行周期中有多个目的。

55. 发明授权

US5420990A Mechanism for enforcing the correct order of instruction execution 失效
标题翻译：执行指令执行顺序的机制
公开(公告)号：US5420990A
公开(公告)日：1995-05-30
申请号：US79494
申请日：1993-06-17
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3834 , G06F9/3842
摘要： An apparatus for enforcing that selected instructions are executed in a correct order, comprising a first content addressable memory for storing load addresses of data read from the memory by the selected instructions. The first content addressable memory comparing the store addresses with the load addresses of data to be written to the memory. The first content addressable memory generating a first signal, if one of the load addresses is identical to a subsequently compared one of the store addresses. The apparatus further including a second content addressable memory for storing and comparing states of the data read and written by the selected instructions. The second content addressable memory generating a second signal, if one of the stored states is identical to one of said compared states. The stored states including a program counter to repeat the execution of the selected instructions upon detecting the first and second signals.
摘要翻译：用于执行所选指令的装置以正确的顺序执行，包括用于存储由所选择的指令从存储器读取的数据的加载地址的第一内容可寻址存储器。第一内容可寻址存储器将存储地址与要写入存储器的数据的加载地址进行比较。所述第一内容可寻址存储器产生第一信号，如果所述加载地址之一与随后比较的一个所述存储地址相同。该装置还包括第二内容可寻址存储器，用于存储和比较由所选指令读和写的数据的状态。如果存储状态之一与所述比较状态之一相同，则第二内容可寻址存储器产生第二信号。所存储的状态包括在检测到第一和第二信号时重复所选指令的执行的程序计数器。

56. 发明授权

US5067069A Control of multiple functional units with parallel operation in a microcoded execution unit 失效
标题翻译：在微型执行单元中并行运行的多功能单元的控制
公开(公告)号：US5067069A
公开(公告)日：1991-11-19
申请号：US306832
申请日：1989-02-03
申请人： Elaine H. Fite , Tryggve Fossum , William R. Grundmann , Francis X. McKeen , Ronald M. Salett
发明人： Elaine H. Fite , Tryggve Fossum , William R. Grundmann , Francis X. McKeen , Ronald M. Salett
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30101 , G06F9/3836 , G06F9/3857 , G06F9/3863 , G06F9/3867 , G06F9/3885
摘要： To increase the performance of a pipelined processor executing various classes of instructions, the classes of instructions are executed by respective functional units which are independently controlled and operated in parallel. The classes of instructions include integer instructions, floating point instructions, multiply instructions, and divide instructions. The integer unit, which also performs shift operations, is controlled by the microcode execution unit to handle the wide variety of integer and shift operations included in a complex, variable-length instruction set. The other functional units need only accept a control command to initiate the operation to be performed by the functional unit. The retiring of the results of the instructions need not be controlled by the microcode execution unit, but instead is delegated to a separate retire unit that services a result queue. When the microcode execution unit determines that a new operation is required, an entry is inserted into the result queue. The entry includes all the information needed by the retire unit to retire the result once the result is available from the respective functional unit. The retire unit services the result queue by reading a tag in the entry at the head of the queue to determine the functional unit that is to provide the result. Once the result is available and the destination specified by the entry is also available, the result is retired in accordance with the entry, and the entry is removed from the queue.

57. 发明授权

US4985825A System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer 失效
标题翻译：用于延迟存储器访问异常的处理的系统，直到基于虚拟存储器系统的数字计算机的指令流水线的执行阶段为止
公开(公告)号：US4985825A
公开(公告)日：1991-01-15
申请号：US306866
申请日：1989-02-03
申请人： David A. Webb, Jr. , David B. Fite , Ricky C. Hetherington , Francis X. McKeen , Mark A. Firstenberg , John E. Murray , Dwight P. Manley , Ronald M. Salett , Tryggve Fossum
发明人： David A. Webb, Jr. , David B. Fite , Ricky C. Hetherington , Francis X. McKeen , Mark A. Firstenberg , John E. Murray , Dwight P. Manley , Ronald M. Salett , Tryggve Fossum
IPC分类号： G06F9/38 , G06F11/07 , G06F12/08 , G06F12/10
CPC分类号： G06F9/3865 , G06F11/073 , G06F11/0772 , G06F12/1045
摘要： A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with storage for virtual addresses accompanying an instruction as well as storage for corresponding fault information. When a memory access exception is encountered at the front end of the memory unit, the fault information generated therefrom is loaded into the storage and the port is prevented from accepting further references.

58. 发明申请

US20140223197A1 METHOD AND APPARATUS FOR MEMORY ENCRYPTION WITH INTEGRITY CHECK AND PROTECTION AGAINST REPLAY ATTACKS 有权
标题翻译：用于内容加密的方法和装置，具有完整的检查和防止重复攻击的保护
公开(公告)号：US20140223197A1
公开(公告)日：2014-08-07
申请号：US13977213
申请日：2011-06-29
申请人： Shay Gueron , Uday Savagaonkar , Francis X. McKeen , Carlos V. Rozas , David M. Durham , Jacob Doweck , Ofir Mulla , Ittai Anati , Zvika Greenfield , Moshe Maor
发明人： Shay Gueron , Uday Savagaonkar , Francis X. McKeen , Carlos V. Rozas , David M. Durham , Jacob Doweck , Ofir Mulla , Ittai Anati , Zvika Greenfield , Moshe Maor
IPC分类号： G06F21/72
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/00 , G06F21/64 , H04L9/0637 , H04L9/3242
摘要： A method and apparatus to provide cryptographic integrity checks and replay protection to protect against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. A tree-based replay protection scheme uses standard XTS-AES to encrypt contents of a cache line in the system memory. A Message-Authentication Code (MAC) for the cache line is encrypted using enhanced XTS-AES and a “time stamp” indicator associated with the cache line. The “time stamp indicator” is stored in a processor.
摘要翻译：提供了一种提供加密完整性检查和重放保护以防止对系统存储器的硬件攻击的方法和装置。分组密码的操作模式增强了标准的XTS-AES操作模式，通过扩展调整以包括“时间戳”指示符来执行存储器加密。基于树的重放保护方案使用标准的XTS-AES来加密系统内存中的高速缓存行的内容。高速缓存行的消息认证码（MAC）使用增强型XTS-AES和与高速缓存行相关联的“时间戳”指示符进行加密。 “时间戳指示符”存储在处理器中。

59. 发明申请

US20130232344A1 TECHNIQUE FOR SUPPORTING MULTIPLE SECURE ENCLAVES 有权
标题翻译：支持多种安全措施的技术
公开(公告)号：US20130232344A1
公开(公告)日：2013-09-05
申请号：US13838237
申请日：2013-03-15
申请人： Simon P. Johnson , Uday R. Savagaonkar , Vincent R. Scarlata , Francis X. McKeen , Carlos V. Rozas
发明人： Simon P. Johnson , Uday R. Savagaonkar , Vincent R. Scarlata , Francis X. McKeen , Carlos V. Rozas
IPC分类号： G06F12/14
CPC分类号： G06F12/1466 , G06F21/53 , G06F21/6218 , G06F21/64 , G06F21/645
摘要： A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
摘要翻译：一种在计算机系统内实现安全应用和数据完整性的技术。在一个实施例中，建立一个或多个安全空间，其中可以存储和执行应用和数据。

60. 发明授权

US08028341B2 Providing extended memory protection 有权
标题翻译：提供扩展的内存保护
公开(公告)号：US08028341B2
公开(公告)日：2011-09-27
申请号：US12606408
申请日：2009-10-27
申请人： Antonio S. Cheng , Francis X. McKeen
发明人： Antonio S. Cheng , Francis X. McKeen
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F12/145 , G06F12/1063
摘要： In one embodiment, the present invention provides for extended memory protection for memory of a system. The embodiment includes a method for associating a protection indicator of a protection record maintained outside of an application's data space with a memory location, and preventing access to the memory location based on the status of the protection indicator. In such manner, more secure operation is provided, as malicious code or other malware is prevented from accessing protected memory locations. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明提供用于系统的存储器的扩展存储器保护。该实施例包括一种用于将维护在应用程序的数据空间外部的保护记录的保护指示符与存储器位置相关联的方法，以及基于保护指示符的状态来阻止对存储器位置的访问。以这种方式，提供更安全的操作，因为防止恶意代码或其他恶意软件访问受保护的存储器位置。描述和要求保护其他实施例。

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