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51. 发明申请

US20120068143A1 Memory Arrays And Methods Of Forming Memory Cells 有权
标题翻译：内存阵列和形成记忆体的方法
公开(公告)号：US20120068143A1
公开(公告)日：2012-03-22
申请号：US12886283
申请日：2010-09-20
申请人： John Smythe , Gurtej S. Sandhu
发明人： John Smythe , Gurtej S. Sandhu
IPC分类号： H01L45/00 , H01L21/16
CPC分类号： H01L45/145 , H01L27/2409 , H01L27/2472 , H01L27/2481
摘要： Some embodiments include methods of forming memory cells utilizing various arrangements of conductive lines, electrodes and programmable material; with the programmable material containing high k dielectric material directly against multivalent metal oxide. Some embodiments include arrays of memory cells, with the memory cells including programmable material containing high k dielectric material directly against multivalent metal oxide.
摘要翻译：一些实施例包括利用导电线，电极和可编程材料的各种布置形成存储单元的方法; 其中可编程材料含有高k电介质材料直接抵抗多价金属氧化物。一些实施例包括存储器单元的阵列，其中存储单元包括直接对抗多价金属氧化物的包含高k电介质材料的可编程材料。

52. 发明授权

US08133664B2 Methods of forming patterns 有权
标题翻译：形成图案的方法
公开(公告)号：US08133664B2
公开(公告)日：2012-03-13
申请号：US12397083
申请日：2009-03-03
申请人： Scott Sills , Gurtej S. Sandhu , John Smythe , Ming Zhang
发明人： Scott Sills , Gurtej S. Sandhu , John Smythe , Ming Zhang
IPC分类号： G03F7/26
CPC分类号： H01L21/0274 , G03F7/20 , G03F7/40 , H01L21/0337 , H01L21/0338
摘要： Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.
摘要翻译：一些实施例包括形成开口图案的方法。所述方法可以包括在衬底上形成间隔的特征。特征可以具有顶部并且可以具有从顶部向下延伸的侧壁。第一材料可以沿着特征的顶部和侧壁形成。第一材料可以通过将特征上的第一材料的共形层旋转浇铸而形成，或通过相对于基底的特征的选择性沉积来形成。在形成第一材料之后，可以在特征之间提供填充材料，同时使第一材料的区域暴露。然后可以相对于填充材料和特征来选择性地去除第一材料的暴露区域以产生开口图案。

53. 发明申请

US20110201211A1 Method and Apparatus Providing Air-Gap Insulation Between Adjacent Conductors Using Nanoparticles 有权
标题翻译：使用纳米颗粒在相邻导体之间提供空气间隙绝缘的方法和装置
公开(公告)号：US20110201211A1
公开(公告)日：2011-08-18
申请号：US13096052
申请日：2011-04-28
申请人： Nishant Sinha , Gurtej Sandhu , Neil Greeley , John Smythe
发明人： Nishant Sinha , Gurtej Sandhu , Neil Greeley , John Smythe
IPC分类号： H01L21/31 , B82Y40/00
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.
摘要翻译：公开了半导体器件及其形成方法，其中至少两个相邻的导体在它们之间具有空隙绝缘体，其被绝缘材料的纳米颗粒覆盖，其尺寸是防止纳米颗粒基本上进入气隙的尺寸。

54. 发明申请

US20100193780A1 METHOD OF FORMING MEMORY CELL USING GAS CLUSTER ION BEAMS 有权
标题翻译：使用气体离子束形成记忆细胞的方法
公开(公告)号：US20100193780A1
公开(公告)日：2010-08-05
申请号：US12365473
申请日：2009-02-04
申请人： John Smythe
发明人： John Smythe
IPC分类号： H01L29/04 , H01L21/20 , H01L21/44 , H01L21/02
CPC分类号： H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.
摘要翻译：一种可变电阻存储单元结构及其形成方法。该方法包括形成第一电极，在第一电极上形成绝缘材料，在绝缘材料中形成通孔以暴露第一电极的表面，在气体簇离子束中形成通孔内的加热材料，形成可变电阻并且形成第二电极，使得加热材料和可变电阻材料设置在第一和第二电极之间。

55. 发明授权

US07737559B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07737559B2
公开(公告)日：2010-06-15
申请号：US11591017
申请日：2006-10-31
申请人： John Smythe
发明人： John Smythe
IPC分类号： H01L29/40 , H01L23/52 , H01L23/48
CPC分类号： H01L21/02126 , H01L21/02211 , H01L21/02222 , H01L21/288 , H01L21/316 , H01L21/32051 , H01L21/76831 , H01L21/76843 , H01L21/76877
摘要： The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise an aluminum-containing compound and one or both of silane and silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
摘要翻译：本发明包括在与半导体衬底相关联的波状表面形貌上保形地形成层的方法。起伏的表面形貌可以首先暴露于氧化钛，氧化钕，氧化钇，氧化锆和氧化钒中的一种或多种以处理表面，并且随后可以暴露于沿着被处理的表面共形形成层的材料。该材料可以例如包含含铝化合物和硅烷和硅氮烷中的一种或两种。本发明还包括在包含氧化钛，氧化钇，氧化锆和氧化钒中的一种或多种的衬垫上形成保形层的半导体结构。

56. 发明授权

US07557047B2 Method of forming a layer of material using an atomic layer deposition process 失效
标题翻译：使用原子层沉积工艺形成材料层的方法
公开(公告)号：US07557047B2
公开(公告)日：2009-07-07
申请号：US11423197
申请日：2006-06-09
申请人： Neal Rueger , John Smythe
发明人： Neal Rueger , John Smythe
IPC分类号： H01L21/31
CPC分类号： C23C16/45525 , C23C16/45536
摘要： Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative embodiment, the method includes identifying a target characteristic for the layer of material, determining a precursor pulse time for introducing a precursor gas into the process chamber during the ALD process to produce the target characteristic in the layer of material, and performing the ALD process that comprises a plurality of steps wherein the precursor gas is introduced into the chamber for the determined precursor pulse time to thereby form the layer of material.
摘要翻译：公开了一种在处理工具的处理室中使用原子层沉积（ALD）工艺形成材料层的方法。在一个说明性实施例中，该方法包括识别材料层的目标特性，确定用于在ALD过程期间将前体气体引入处理室的前体脉冲时间，以在材料层中产生目标特性，并执行 ALD方法，其包括多个步骤，其中将前体气体引入到室中用于所确定的前体脉冲时间，从而形成材料层。

57. 发明授权

US07262135B2 Methods of forming layers 有权
标题翻译：形成层的方法
公开(公告)号：US07262135B2
公开(公告)日：2007-08-28
申请号：US11218233
申请日：2005-09-01
申请人： John Smythe
发明人： John Smythe
IPC分类号： H01L21/44
CPC分类号： H01L21/02126 , H01L21/02211 , H01L21/02222 , H01L21/288 , H01L21/316 , H01L21/32051 , H01L21/76831 , H01L21/76843 , H01L21/76877
摘要： The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise an aluminum-containing compound and one or both of silane and silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
摘要翻译：本发明包括在与半导体衬底相关联的波状表面形貌上共形形成层的方法。起伏的表面形貌可以首先暴露于氧化钛，氧化钕，氧化钇，氧化锆和氧化钒中的一种或多种以处理表面，并且随后可以暴露于沿着被处理的表面共形形成层的材料。该材料可以例如包含含铝化合物和硅烷和硅氮烷中的一种或两种。本发明还包括在包含氧化钛，氧化钇，氧化锆和氧化钒中的一种或多种的衬垫上形成保形层的半导体结构。

58. 发明申请

US20070049003A1 Semiconductor constructions and methods of forming layers 有权
标题翻译：半导体结构和形成层的方法
公开(公告)号：US20070049003A1
公开(公告)日：2007-03-01
申请号：US11218233
申请日：2005-09-01
申请人： John Smythe
发明人： John Smythe
IPC分类号： H01L21/4763
CPC分类号： H01L21/02126 , H01L21/02211 , H01L21/02222 , H01L21/288 , H01L21/316 , H01L21/32051 , H01L21/76831 , H01L21/76843 , H01L21/76877
摘要： The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
摘要翻译：本发明包括在与半导体衬底相关联的波状表面形貌上保形地形成层的方法。起伏的表面形貌可以首先暴露于氧化钛，氧化钕，氧化钇，氧化锆和氧化钒中的一种或多种以处理表面，并且随后可以暴露于沿着被处理的表面共形形成层的材料。该材料可以例如包括铝硅烷和铝硅氮烷中的一种或两种。本发明还包括在包含氧化钛，氧化钇，氧化锆和氧化钒中的一种或多种的衬垫上形成保形层的半导体结构。

59. 发明申请

US20060265868A1 Inter-metal dielectric fill 审中-公开
公开(公告)号：US20060265868A1
公开(公告)日：2006-11-30
申请号：US11487027
申请日：2006-07-14
申请人： Neal Rueger , Chris Hill , Zailong Bian , John Smythe
发明人： Neal Rueger , Chris Hill , Zailong Bian , John Smythe
IPC分类号： H01R43/00
CPC分类号： H01L21/76837 , H01L21/76834 , H01L23/53223 , H01L23/53295 , H01L2924/0002 , Y10T29/49117 , H01L2924/00
摘要： An inter-metal dielectric (IMD) fill process includes depositing an insulating nanolaminate barrier layer. The nanolaminate is preferably an oxide liner formed by using an alternating layer deposition process. The layer is highly conformal and is an excellent diffusion barrier. Gaps between metal lines are filled using high density plasma chemical vapor deposition with a reactive species gas. The barrier layer protects the metal lines from shorts between neighboring layers. The resulting structure has substantially uneroded metal lines and an insulating IMD fill.

60. 发明授权

US08691622B2 Memory cells and methods of forming memory cells 有权
公开(公告)号：US08691622B2
公开(公告)日：2014-04-08
申请号：US13480610
申请日：2012-05-25
申请人： John Smythe , Gurtej S. Sandhu
发明人： John Smythe , Gurtej S. Sandhu
IPC分类号： H01L21/06 , H01L21/311
CPC分类号： H01L45/12 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/16 , H01L45/1675
摘要： A method of forming a memory cell includes forming programmable material within an opening in dielectric material over an elevationally inner conductive electrode of the memory cell. Conductive electrode material is formed over the dielectric material and within the opening. The programmable material within the opening has an elevationally outer edge surface angling elevationally and laterally inward relative to a sidewall of the opening. The conductive electrode material is formed to cover over the angling surface of the programmable material within the opening. The conductive electrode material is removed back at least to an elevationally outermost surface of the dielectric material and to leave the conductive electrode material covering over the angling surface of the programmable material within the opening. The conductive electrode material constitutes at least part of an elevationally outer conductive electrode of the memory cell. Memory cells independent of method of manufacture are also disclosed.

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