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51. 发明授权

US06753247B1 Method(s) facilitating formation of memory cell(s) and patterned conductive 失效
标题翻译：促进形成记忆体和图案化的导电聚合物膜的方法
公开(公告)号：US06753247B1
公开(公告)日：2004-06-22
申请号：US10285183
申请日：2002-10-31
申请人： Uzodinma Okoroanyanwu , Suzette K. Pangrle , Matthew S. Buynoski , Nicholas H. Tripsas , Mark S. Chang , Ramkumar Subramanian , Angela T. Hui
发明人： Uzodinma Okoroanyanwu , Suzette K. Pangrle , Matthew S. Buynoski , Nicholas H. Tripsas , Mark S. Chang , Ramkumar Subramanian , Angela T. Hui
IPC分类号： H01L214763
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L27/285
摘要： A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is applied over the stack to at least fill in the first via. A second via is then etched into the dielectric material so as to expose and make the electrode layer available as a top electrode. A wordline is then formed over the dielectric material such that the top electrode is connected to the wordline by way of the second via. A memory device formed in accordance with the disclosed methodology includes a top electrode formed over an organic polymer layer, a conductive layer under the organic polymer layer, a via defined by a dielectric material and located above the top electrode, and a wordline formed over the dielectric material such that the top electrode is connected to the wordline by way of the via.
摘要翻译：公开了一种用于形成存储单元的方法，其中在导电层上形成有机聚合物层，并且在有机聚合物层上形成电极层。将第一通孔蚀刻到电极和有机聚合物层中，并且将电介质材料施加到堆叠上以至少填充在第一通孔中。然后将第二通道蚀刻到电介质材料中，以暴露并使电极层可用作顶部电极。然后在电介质材料上形成字线，使得顶部电极通过第二通孔连接到字线。根据所公开的方法形成的存储器件包括形成在有机聚合物层上的顶部电极，有机聚合物层下面的导电层，由电介质材料限定并位于顶部电极之上的通孔，以及形成在上部电极上的字线电介质材料，使得顶部电极通过通孔连接到字线。

52. 发明授权

US06171919B2 MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation 有权
标题翻译： MOS晶体管形成工艺包括用于改善硅化物形成的后间隔蚀刻表面处理
公开(公告)号：US06171919B2
公开(公告)日：2001-01-09
申请号：US09361155
申请日：1999-07-27
申请人： Paul R. Besser , Minh Van Ngo , Simon S. Chan , Angela T. Hui
发明人： Paul R. Besser , Minh Van Ngo , Simon S. Chan , Angela T. Hui
IPC分类号： H01L21336
CPC分类号： H01L29/665
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.
摘要翻译：通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣。实施例包括通过进行氢离子等离子体处理来除去碳质残渣。

53. 发明授权

US08367493B1 Void free interlayer dielectric 有权
标题翻译：无空隙层间电介质
公开(公告)号：US08367493B1
公开(公告)日：2013-02-05
申请号：US11109719
申请日：2005-04-20
申请人： Minh Van Ngo , Hirokazu Tokuno , Angela T. Hui , Wenmei Li , Hsiao-Han Thio
发明人： Minh Van Ngo , Hirokazu Tokuno , Angela T. Hui , Wenmei Li , Hsiao-Han Thio
IPC分类号： H01L21/8238
CPC分类号： H01L23/291 , H01L21/823425 , H01L21/823475 , H01L27/11521 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.
摘要翻译：一种制造非易失性存储器件的方法包括形成多个存储单元。该方法还包括在存储器单元上沉积第一介电层，其中第一介电层是具有基本均匀厚度的共形层。该方法还包括在第一介电层上沉积第二电介质层。第一和第二电介质层一起形成没有空隙的层间电介质。

54. 发明授权

US08283718B2 Integrated circuit system with metal and semi-conducting gate 有权
标题翻译：具有金属和半导体栅极的集成电路系统
公开(公告)号：US08283718B2
公开(公告)日：2012-10-09
申请号：US11611856
申请日：2006-12-16
申请人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
发明人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

55. 发明申请

US20120032308A1 GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS 有权
标题翻译：使用蚀刻或干蚀刻方法对选定的晶体管的目标光盘进行栅格扫描过程
公开(公告)号：US20120032308A1
公开(公告)日：2012-02-09
申请号：US13278343
申请日：2011-10-21
申请人： Bradley M. Davis , Jihwan Choi , Angela T. Hui
发明人： Bradley M. Davis , Jihwan Choi , Angela T. Hui
IPC分类号： H01L21/306 , H01L29/06
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28132 , H01L21/823456
摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.
摘要翻译：公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

56. 发明申请

US20110195578A1 PLANAR CELL ON CUT USING IN-SITU POLYMER DEPOSITION AND ETCH 有权
标题翻译：使用现场聚合物沉积和蚀刻的切片的平面细胞
公开(公告)号：US20110195578A1
公开(公告)日：2011-08-11
申请号：US12703586
申请日：2010-02-10
申请人： Angela T. Hui , Gang Xue
发明人： Angela T. Hui , Gang Xue
IPC分类号： H01L21/3065
CPC分类号： H01L27/11568 , H01L27/11565
摘要： A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.
摘要翻译：提供了一种电荷存储层分离的方法和制造方法。诸如聚合物层的层沉积在ONO层的顶部上，使得聚合物层被平坦化或近似平坦化。 ONO包括至少第一区域和第二区域，其中第一区域高于第二区域。例如，第一区域可以是在源极/漏极区域上的ONO的部分，并且第二区域可以是在浅沟槽上的ONO的部分。在聚合物层上进行蚀刻以暴露ONO层的第一区域，留下ONO的第二区域未曝光。蚀刻继续发生以蚀刻在第一区域处的暴露的ONO，使得ONO层在第一区域被蚀刻掉，并且第二区域保持未曝光。

57. 发明申请

US20080150042A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 有权
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080150042A1
公开(公告)日：2008-06-26
申请号：US11958254
申请日：2007-12-17
申请人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
发明人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11521
摘要： A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在间隔物上形成阻挡金属层，并形成金属插塞外部掺杂区域和阻挡金属层。

58. 发明授权

US07115440B1 SO2 treatment of oxidized CuO for copper sulfide formation of memory element growth 有权
标题翻译： SO2处理氧化CuO对硫化铜形成记忆元素生长
公开(公告)号：US07115440B1
公开(公告)日：2006-10-03
申请号：US10957247
申请日：2004-10-01
申请人： Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , James J. Xie , Angela T. Hui
发明人： Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , James J. Xie , Angela T. Hui
IPC分类号： H01L21/00
CPC分类号： H01L51/0575 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/77 , H01L27/285 , H01L51/105
摘要： Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve oxidizing a portion of a copper containing electrode to form a copper oxide layer; contacting the copper oxide layer with at least one of a sulfur containing gas or plasma to form a CuS layer; forming an organic semiconductor over the CuS layer; and forming an electrode over the organic semiconductor. Such devices containing the memory cells are characterized by light weight and robust reliability.
摘要翻译：公开了制造存储单元和包含存储单元的半导体器件的方法。所述方法包括氧化一部分含铜电极以形成氧化铜层; 使所述氧化铜层与含硫气体或等离子体中的至少一种接触以形成CuS层; 在CuS层上形成有机半导体; 并在有机半导体上形成电极。包含存储器单元的这种器件的特征在于重量轻和鲁棒的可靠性。

59. 发明授权

US06593632B1 Interconnect methodology employing a low dielectric constant etch stop layer 有权
标题翻译：采用低介电常数蚀刻停止层的互连方法
公开(公告)号：US06593632B1
公开(公告)日：2003-07-15
申请号：US09375500
申请日：1999-08-17
申请人： Steven C. Avanzino , Minh Van Ngo , Angela T. Hui , Chun Jiang , Hamid Partovi
发明人： Steven C. Avanzino , Minh Van Ngo , Angela T. Hui , Chun Jiang , Hamid Partovi
IPC分类号： H01L2976
CPC分类号： H01L21/76895 , H01L21/3148 , H01L21/76834 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： The capacitance between the gate of a transistor and local interconnect is reduced employing SiC as an etch stop layer. Embodiments include depositing a SiC etch stop layer having a thickness of about 500-1000 Å and a dielectric constant of less than about 3.2, thereby providing a composite dielectric constant between the gate and local interconnect of between about 3.7 to about 4.7. The SiC etch stop layer can be deposited by PECVD or HDP techniques.
摘要翻译：使用SiC作为蚀刻停止层，减小晶体管的栅极和局部互连之间的电容。实施例包括沉积具有约500-1000的厚度和小于约3.2的介电常数的SiC蚀刻停止层，从而在栅极和局部互连之间提供约3.7至约4.7的复合介电常数。 SiC蚀刻停止层可以通过PECVD或HDP技术沉积。

60. 发明授权

US06501555B1 Optical technique to detect etch process termination 有权
标题翻译：检测蚀刻工艺终止的光学技术
公开(公告)号：US06501555B1
公开(公告)日：2002-12-31
申请号：US09773954
申请日：2001-02-01
申请人： Kouros Ghandehari , Bhanwar Singh , Angela T. Hui
发明人： Kouros Ghandehari , Bhanwar Singh , Angela T. Hui
IPC分类号： G01B1128
CPC分类号： H01L22/26 , H01L22/12
摘要： The disclosure describes an exemplary method of detecting a process end point during etching in the fabrication of an integrated circuit. This method can include receiving a reference signal indicative of an intensity of a light source, collecting a reflection signal reflected off a surface of an integrated circuit wafer, and comparing the reference signal and the reflection signal to locate absorption bands, the absorption band being indicative of a process end point.
摘要翻译：本公开描述了在集成电路的制造中在蚀刻期间检测处理终点的示例性方法。该方法可以包括接收指示光源强度的参考信号，收集从集成电路晶片的表面反射的反射信号，以及比较参考信号和反射信号以定位吸收带，吸收带指示的过程终点。

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