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51. 发明专利

CA2466463A1 METHOD AND SYSTEM FOR VIDEO AND AUXILIARY DATA TRANSMISSION OVER A SERIAL LINK 未知
公开(公告)号：CA2466463A1
公开(公告)日：2003-07-17
申请号：CA2466463
申请日：2002-12-05
申请人： SILICON IMAGE INC
发明人： KEATING STEPHEN J , SIEMENS DUANE , BANKS JOHN D , WOLF PAUL DANIEL , JUNG KEEWOOK , LYLE JAMES D , AHN GIJUNG , GREKHOV VLADIMIR , HWANG SEUNG HO , SCHUMACHER MICHAEL ANTHONY , SCALISE ALBERT M , LEE ERIC
IPC分类号： H04N7/08 , H04L1/00 , H04L1/20 , H04L9/20 , H04L25/49 , H04N20060101 , H04N1/00 , H04N7/081 , H04N7/52 , H04N7/66
摘要： A communication system including a transmitter (1~), a receiver (2~), and a serial link, in transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one of more channels of the link during data islands between bursts of encoded video dat a. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link.

52. 发明专利

DE69626211D1 未知
公开(公告)号：DE69626211D1
公开(公告)日：2003-03-20
申请号：DE69626211
申请日：1996-10-01
申请人： SILICON IMAGE INC
发明人： SHIN YESHIK , LEE KYEONGHO , KIM SUNGJOON , LEE D
IPC分类号： H04N7/08 , G09G3/20 , G09G5/00 , H03M5/14 , H03M7/14 , H04L7/00 , H04L7/04 , H04L25/02 , H04L25/08 , H04L25/49 , H04N7/081 , H04N7/083 , H04N7/52 , H04N21/2368 , H04N21/434
摘要： A new high-speed digital interface for transmitting video information over various transmission media including terminated copper wires such as twisted-pair wires and fiber optical cable is described. The significance of this new interface is that (1) it only uses a small number of data channels with all timing and control data embedded in data transmission, (2) it uses a transition controlled binary DC balanced coding for reliable, low-power and high-speed data transmission, (3) it uses low-swing differential voltage which minimizes EMI, and (4) it can be implemented in low-cost scaleable CMOS technology as a megacell or standard IC. The high-speed digital interface incorporates a method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.

53. 发明专利

DK0978115T3 未知
公开(公告)号：DK0978115T3
公开(公告)日：2002-07-01
申请号：DK97939627
申请日：1997-08-27
申请人： SILICON IMAGE INC
发明人： COSTA VICTOR M DA
IPC分类号： G09G3/20 , G09G3/36
摘要： A smart controller chip for controlling an active matrix display. Within the controller chip, circuitry for generating analog reference levels is incorporated alongside circuitry for generating digital timing and control signals. The combination of D/A analog circuitry and standard digital logic makes the controller uniquely suited for addressing all the panel control needs both for the normal digital functions but also for control of the analog aspects of the panel, like display gamma. The analog reference levels and the digital signals are made programmable using registers internal to the controller chip. The contents of these registers are programmed initially by digital values stored in an external PROM or in flash memory integrated into the controller chip. In addition, software in a host system is able to program these registers via an interface between the host system and the controller chip.

54. 发明专利

DE69619560D1 未知
公开(公告)号：DE69619560D1
公开(公告)日：2002-04-04
申请号：DE69619560
申请日：1996-09-30
申请人： SILICON IMAGE INC
发明人： SHIN YESHIK , LEE KYEONGHO , KIM SUNGJOON , LEE DAVID
IPC分类号： H03M7/14 , H04L7/00 , H04L7/04 , H04L25/03 , H04L25/08 , H04L25/49 , H04N7/083 , H04N7/52
摘要： A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.

55. 发明专利

AU8855901A Data recovery using data eye tracking 未知
公开(公告)号：AU8855901A
公开(公告)日：2002-03-13
申请号：AU8855901
申请日：2001-08-30
申请人： SILICON IMAGE INC
发明人： LEE SANG-HYUN , JEONG DEOG-KYOON
IPC分类号： H03L7/08 , H03L7/081 , H03L7/091 , H04L7/02 , H04L7/033 , H04L25/02
摘要： A data recovery system for a serial digital data link includes a data sampler, compare logic, a phase controller, and a phase shifter. The data sampler samples input data three times in a bit time which time is determined by clock pulses generated by the phase shifter, and recovers digital data according to a predetermined decision criterion. The compare logic compares the output of the data sampler according to a predetermined method. Phase controller uses the output of the compare logic and generates phase control signals. The phase shifter uses the phase control signals and makes three different phase clocks from input clock. The input clock can be an external clock, or can be recovered from the external clock or input data stream.

56. 发明专利

CA2354780A1 DIGITAL DISPLAY JITTER CORRECTION APPARATUS AND METHOD 未知
公开(公告)号：CA2354780A1
公开(公告)日：2002-02-04
申请号：CA2354780
申请日：2001-08-03
申请人： SILICON IMAGE INC
发明人： KEATING STEPHEN J , MARTIN RUSSEL A , DA COSTA VICTOR M , KIM GYUDONG
IPC分类号： H03K5/13 , H04L7/02 , H04N5/208 , H04N5/21
摘要： A fitter correction apparatus and method are disclosed. In one embodiment, t he apparatus has a rising edge corrector to receive a jittered signal and to output a fitter corrected rising edge of the jittered signal. The apparatus may also have a falling ed ge corrector to receive the jittered signal and to output a fitter corrected falling edge of the jittered signal. The fitter correction apparatus may include an output device to receive the fitter corrected rising edge, to receive the fitter corrected falling edge, and to output a fitter corrected signal.

57. 发明专利

CA2309519A1 METHODS AND SYSTEMS FOR TMDS ENCRYPTION 未知
公开(公告)号：CA2309519A1
公开(公告)日：2000-11-28
申请号：CA2309519
申请日：2000-05-26
申请人： SILICON IMAGE INC
发明人： KIM GYUDONG , DA COSTA VICTOR M , MARTIN RUSSEL A , HWANG SEUNG HO , LEE DAVID D , KIM BRUCE
IPC分类号： H04L9/34
摘要： The present invention is directed io systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of a) performing transition controlled encoding of a fast sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to produce masked n+1 bit data characters; c) DC balancing the masked n+l bit data characters to produce DC balanced, masked n+2 bit data characters; d) scrambling the DC balanced, masked n+2 bit data characters using a scrambling formula to produce encrypted n+2 bit data characters; e) encoding control data into encoded n+2 bit control characters, f) generating a serial data stream in response to the encrypted data characters and encoded control characters, and g) transmitting the serial data stream over a communication link. Subsequent to step (e) and prior to step (f), the method can further include the step of encrypting the encoded n+2 bit control characters, such that the generating step generates a serial data stream in response to the encrypted data characters and the encrypted control characters.

58. 发明专利

CA2343814A1 BI-DIRECTIONAL DATA TRANSFER USING TWO PAIR OF DIFFERENTIAL LINES AS A SINGLE ADDITIONAL DIFFERENTIAL PAIR 未知
公开(公告)号：CA2343814A1
公开(公告)日：2000-03-23
申请号：CA2343814
申请日：1999-09-10
申请人： SILICON IMAGE INC
发明人： MARTIN RUSSEL A
IPC分类号： H04L25/02 , G06F3/14 , G09G5/00 , H04L5/20
摘要： Data is transferred from a processor to a display in one direction. However, there are many reasons for data to be transferred in both directions along a cable connecting the processor and display. This invention describes a metho d of sending data from the display back to the processor computer in a situati on in which the video data transferred to the display is in digital form. Differential wire pairs are used to transmit red, green and blue digital pix el data in a first direction from the processor to the display using a high common mode rejection ratio in each of the twisted wire differential pairs. Using this common mode, digital data may be serially transmitted in a revers e direction from the display. The common mode is offset between two of the twisted wire differential pairs by varying the DC offset or reference voltag e in one of the twisted wire differential pairs relative to the other differential pair. Both wires in a pair have their DC offset adjusted to as not to affect digital pixel data transmitted in a forward direction. DC offsets in each pair are compared, with a change in DC offset of one pair us ed for transmitting a logic high and a change in the DC offset of the other pai r used for transmitting a logic low. In this way, bi-directional data transfer is accomplished without increasing the number of twisted wire pairs coupled between the processor and display.

59. 发明专利

CA2334111A1 DISPLAY MODULE DRIVING SYSTEM COMPRISING DIGITAL TO ANALOG CONVERTERS 未知
公开(公告)号：CA2334111A1
公开(公告)日：1999-12-09
申请号：CA2334111
申请日：1999-06-04
申请人： SILICON IMAGE INC
发明人： KIM EUN-GU
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： A display module driving system wherein digital pixel data for an image to b e displayed is provided to a plurality of column drivers on a row by row basis in serial format over a plurality of dedicated bus lines rather than a singl e parallel bus line. Digital pixel data for a complete image row is divided in to segments, wherein the number of segments is each to the number of column drivers. Each segment is then serialized and transmitted to a corresponding column driver such that the digital pixel data for an entire row is transferred to each of the plurality of column drivers at the same time. The column drivers receive the segments and rearrange the data into parallel. Th e pixels are then transferred to a digital to analog converter, preferably two pixels at a time, where each pixel is converted into analog red, green and blue signals. An analog sample and hold module samples each analog signal fo r all of the pixels in a given row of the display and stores the signals in first capacitors of a plurality of sample and hold capacitor pairs. The samp le and hold capacitor pairs allow analog signals to be sampled and held on a ro w by row basis such that when one capacitor in each pair stores one of the analog red, green and blue voltages for a subsequent row, the other capacito r transfers theanalog voltage signal out for a current row to the column electrodes of the display.

60. 发明专利

AU3448799A Spread spectrum phase modulation for suppression of electromagnetic interferencein parallel data channels 未知
公开(公告)号：AU3448799A
公开(公告)日：1999-08-09
申请号：AU3448799
申请日：1999-01-20
申请人： SILICON IMAGE INC
发明人： MOON YONGSAM , JEONG DEOG-KYOON , KIM GYUDONG
IPC分类号： G06F1/04 , H04B1/707 , H04B15/00 , H04B15/04
摘要： A new spread spectrum phase modulation (SSPM) technique is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.

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