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51. 发明申请

WO2007089207A1 METHODS FOR MAKING A STARTING SUBSTRATE WAFER FOR SEMICONDUCTOR ENGINEERING HAVING WAFER THROUGH CONNECTIONS 审中-公开
标题翻译：用于通过连接形成半导体工程的启动基板波形的方法
公开(公告)号：WO2007089207A1
公开(公告)日：2007-08-09
申请号：PCT/SE2007/050053
申请日：2007-01-31
申请人： SILEX MICROSYSTEMS AB , KÄLVESTEN, Edvard , BAUER, Tomas
发明人： KÄLVESTEN, Edvard , BAUER, Tomas
IPC分类号： H01L21/768 , H01L23/48 , H01L23/498 , H01L23/532
CPC分类号： H01L23/49827 , H01L21/76898 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistiviy material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections(140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resisitivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).
摘要翻译：本发明涉及一种通过连接（140; 192）制造具有电晶片的用于半导体工程的起始衬底晶片的方法。它包括提供具有前侧和后侧的具有低电阻率硅基底和前侧的高电阻率材料层的晶片（110,150）。在晶片上，在高电阻率材料层中存在低电阻材料岛。这些岛与硅基材料接触。沟槽从晶片的背面蚀刻，但并不全部穿过晶片，以提供通过连接（140; 192）限定晶片的绝缘外壳。沟槽填充有绝缘材料。然后研磨晶片的前侧以露出绝缘材料，以通过连接产生晶片。还提供了一种用于制造集成电子电路和/或部件的晶片衬底，其包括具有适于半导体工程的高电阻率顶层（122）的低电阻率硅基底（110），其特征在于具有低电阻率晶圆通过连接（140 ）。

52. 发明申请

WO2007070004A2 METHODS FOR MAKING MICRO NEEDLES AND APPLICATIONS THEREOF 审中-公开
标题翻译：制作微针的方法及其应用
公开(公告)号：WO2007070004A2
公开(公告)日：2007-06-21
申请号：PCT/SE2006/050582
申请日：2006-12-14
申请人： SILEX MICROSYSTEMS AB , KÄLVESTEN, Edvard , EBEFORS, Thorbjörn , CORMAN, Thierry
发明人： KÄLVESTEN, Edvard , EBEFORS, Thorbjörn , CORMAN, Thierry
IPC分类号： A61B5/042 , A61B5/151 , A61B5/153 , A61M25/06 , A61M37/00 , A61M5/158 , A61N1/18 , G01N33/483
CPC分类号： A61M37/0015 , A61B5/053 , A61B5/150022 , A61B5/150282 , A61B5/150984 , A61M2037/003 , A61M2037/0046 , A61M2037/0053 , A61N1/0502 , A61N1/0551 , H01L2224/48091 , H01L2224/8592 , H01L2924/00014
摘要： The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.
摘要翻译：本发明在一般方面涉及在衬底上制造垂直突出元件的方法，所述元件具有包括至少一个倾斜表面的尖端和在所述基底和所述尖端之间延伸的细长主体部分。该方法包括形成所述倾斜表面的各向异性的晶面依赖蚀刻; 以及形成所述细长主体部分的各向异性非晶面依赖蚀刻; 结合限定所述突出元件的合适的图案化工艺具有预定的基部几何形状。

53. 发明申请

WO2003069389A1 THREE DIMENSIONAL ALIGNMENT METHOD AND SYSTEM 审中-公开
标题翻译：三维对齐方法与系统
公开(公告)号：WO2003069389A1
公开(公告)日：2003-08-21
申请号：PCT/SE2003/000253
申请日：2003-02-14
申请人： SILEX MICROSYSTEMS AB , KÄLVESTEN, Edvard , EBEFORS, Thorbjörn , GRISS, Patrick , HAASL, Sjoerd , SOHLSTRÖM, Hans , STEMME, Göran
发明人： KÄLVESTEN, Edvard , EBEFORS, Thorbjörn , GRISS, Patrick , HAASL, Sjoerd , SOHLSTRÖM, Hans , STEMME, Göran
IPC分类号： G02B6/42
CPC分类号： G02B6/4238 , G02B6/4225 , G02B6/4226 , G02B6/4227
摘要： ABSTRACTA system for achieving fixation of one or more moveable micro machined platforms for passively aligned optical components, comprising - a support structure containing structures for passive alignment of optical components- platform(s) containing structures for passive alignment of optical components- actuators for actively aligning the already passively aligned components on the platform(s) and the support structure to each other, where the actuators are strong enough while actuating to keep the platform(s) steady during fixation and weak enough while not actuating so as not to impede the fixation- a fixation mechanism to fixate the moveable platform(s) to the support structure.
摘要翻译：用于实现用于被动对准的光学部件的一个或多个可移动微加工平台的固定的ABSTRACTA系统，包括：包含用于光学部件的被动对准的结构的支撑结构 - 包含用于光学部件的被动对准的结构的平台 - 用于主动对准已被动地平台上的对准部件和支撑结构彼此相对，其中致动器足够坚固，同时致动以在固定期间保持平台稳定，并且在不致动的同时足够弱以便不妨碍固定 - 固定机构来固定可移动平台到支撑结构。

54. 发明申请

WO2003068669A1 DEFLECTABLE MICROSTRUCTURE AND METHOD OF MANUFACTURING THE SAME THROUGH BONDING OF WAFERS 审中-公开
标题翻译：可忽略的微结构及其通过结合接合制造相同的方法
公开(公告)号：WO2003068669A1
公开(公告)日：2003-08-21
申请号：PCT/SE2003/000252
申请日：2003-02-14
申请人： SILEX MICROSYSTEMS AB , KÄLVESTEN, Edvard , EBEFORS, Thorbjörn , SVEDIN, Niklas , WESTIN, Håkan
发明人： KÄLVESTEN, Edvard , EBEFORS, Thorbjörn , SVEDIN, Niklas , WESTIN, Håkan
IPC分类号： B81B3/00
CPC分类号： B81C1/0015 , B81B2201/042 , B81C1/00142 , B81C3/002 , B81C2201/019 , B81C2201/0191 , B81C2203/058
摘要： The invention relates to a method of making a deflectable, free hanging micro structure comprising at least one hinge member, the method comprising the steps of providing a first sacrificial wafer comprising a single crystalline material constituting material forming the micro structure. A second semiconductor wafer comprising necessary components for forming the structure in cooperation with said first wafer is provided. Finite areas of a structured bonding material is provided, on one or both of said wafers at selected locations, said finite areas defining points of connection for joining said wafers. The wafers are bonded using heat and optionally pressure. Sacrificial material is etched away from said sacrificial wafer, patterning the top wafer by lithography is performed to define the desired deflectable microstructures having hinges, and subsequently silicon etch to make the structures.
摘要翻译：本发明涉及一种制造包括至少一个铰链构件的可偏转的自由悬挂微结构的方法，所述方法包括以下步骤：提供包括构成微结构的单晶材料构成材料的第一牺牲晶片。提供了包括与所述第一晶片协作形成所述结构的必要部件的第二半导体晶片。在选定位置的一个或两个所述晶片上提供结构化接合材料的有限区域，所述有限区域限定用于连接所述晶片的连接点。使用热和任选的压力将晶片接合。牺牲材料被蚀刻离开所述牺牲晶片，通过光刻来图案化顶部晶片以限定具有铰链的期望的可偏转微结构，并随后进行硅蚀刻以制造结构。

55. 发明申请

WO2003034016A1 PRESSURE SENSOR 审中-公开
标题翻译：压力传感器
公开(公告)号：WO2003034016A1
公开(公告)日：2003-04-24
申请号：PCT/SE2002/001884
申请日：2002-10-15
申请人： SILEX MICROSYSTEMS AB , RANGSTEN, Pelle , KÄLVESTEN, Edvard , MECHBACH, Marianne
发明人： RANGSTEN, Pelle , KÄLVESTEN, Edvard , MECHBACH, Marianne
IPC分类号： G01L9/00
CPC分类号： G01L9/0042 , G01L9/0055 , Y10T29/49002 , Y10T29/49004 , Y10T29/49007
摘要： In manufacturing a pressure sensor a recess that will form part of the sensor cavity is formed in a lower silicon substrate. An SOI-wafer having a monocrystalline silicon layer on top of a substrate is bonded to the lower silicon substrate closing the recess and forming the cavity. The supporting substrate of the SOI-wafer is then etched away, the portion of the monocrystalline layer located above the recess forming the sensor diaphragm. The oxide layer of the SOI-wafer here acts as an "ideal" etch stop in the case where the substrate wafer is removed by dry (plasma) or wet etching using e.g. KOH. This is due to high etch selectivity between silicon and oxide for some etch processes and it results in a diaphragm having a very accurately defined and uniform thickness.The cavity is evacuated by forming a opening to the cavity and then sealing the cavity by closing the opening using LPCVD. Sensor paths for sensing the deflection of the diaphragm are applied on the outer or inner surface of the diaphragm. The monocrystalline diphragm gives the sensor a good long-term stability. Also the sensor path can be made of monocrystalline material, this giving the sensor even better good long-term characteristics. An increased sensitivity can be obtained by making active portions of the sensor paths freely extending, unsupported by other material of the pressure sensor, by suitable etching procedures.
摘要翻译：在制造压力传感器时，形成传感器腔的一部分的凹部形成在下硅衬底中。在衬底顶部具有单晶硅层的SOI晶片被接合到下硅衬底上，封闭凹部并形成空腔。然后蚀刻掉SOI晶片的支撑衬底，单晶层的部分位于形成传感器膜片的凹部之上。 SOI晶片的氧化物层在此通过干式（等离子体）或湿式蚀刻方式除去基板晶片的情况下，作为“理想的”蚀刻停止。 KOH。这是由于在一些蚀刻工艺中硅和氧化物之间的高蚀刻选择性，并且其导致具有非常精确限定和均匀厚度的膜片。通过形成到空腔的开口然后通过闭合开口来密封空腔来抽空空腔使用LPCVD。用于感测隔膜偏转的传感器路径被施加在隔膜的外表面或内表面上。单晶diphragm给传感器良好的长期稳定性。此外，传感器路径也可以由单晶材料制成，这给传感器带来更好的长期特性。传感器路径的有效部分通过适当的蚀刻程序自由延伸，不受压力传感器的其他材料支撑，可以获得增加的灵敏度。

56. 发明授权

EP2901475B1 METHOD FOR FORMING A THROUGH-SILICON VIA BY ELECTROLESS METAL DEPOSITION, AND CORRESPONDING SEMICONDUCTOR DEVICE 无效
公开(公告)号：EP2901475B1
公开(公告)日：2020-02-26
申请号：EP13841291.1
申请日：2013-09-27
申请人： Silex Microsystems AB
发明人： EBEFORS, Thorbjörn , KNUTSSON, Henrik
IPC分类号： H01L21/48 , H01L21/768 , H01L23/48 , H01L23/498 , H01L21/288

57. 发明公开

EP3102534A1 CONTROLLING PRESSURE IN CAVITIES ON SUBSTRATES 审中-公开
标题翻译：压力控制龋洞对基质
公开(公告)号：EP3102534A1
公开(公告)日：2016-12-14
申请号：EP15745967.8
申请日：2015-02-06
申请人： Silex Microsystems AB
发明人： WESTIN, Håkan , WICKERT, Peter
IPC分类号： B81C1/00 , B81B1/00
CPC分类号： B81C1/00293
摘要： The invention relates to a new method of providing different and controlled atmospheres inside cavities on one and the same chip of a MEMS device. With the new method one can refrain from providing separate getter materials, and thereby the manufacturing is simplified. The method comprises providing a first substrate (20) and a second substrate (28) and making at least one depression (22', 22'') in at least one of the substrates(20). A structural component (26) is provided in or on a surface of at least one of the substrates, said structure containing entrapped, absorbed or adsorbed ions, molecules or atoms of a gas. The substrates are bonded together such that a cavity forms and becomes hermetically sealed. The obtained structure is subjected to conditions so as to release the implanted, absorbed or adsorbed gas atoms, ions or molecules from the substrate to provide said controlled atmosphere inside the cavity.

58. 发明公开

EP3038974A1 THIN CAPPING FOR MEMS DEVICES 无效
标题翻译： DÜNNERVERSCHLUSSFÜRMEMS-VORRICHTUNGEN
公开(公告)号：EP3038974A1
公开(公告)日：2016-07-06
申请号：EP14839979.3
申请日：2014-08-26
申请人： Silex Microsystems AB
发明人： KÄLVESTEN, Edvard , EBEFORS, Thorbjörn , SVEDIN, Niklas
IPC分类号： B81B7/00 , B81C1/00 , H01L21/50 , H01L23/48
CPC分类号： B81B7/007 , B81B2201/01 , B81B2201/0264 , B81B2201/0271 , B81B2203/0118 , B81B2203/0127 , B81B2207/095 , B81C1/00301 , B81C2201/0153 , B81C2201/036 , B81C2203/0109 , B81C2203/0145 , H01L21/50 , H01L23/08 , H01L24/94 , H01L2924/16235
摘要： The invention relates to a device comprising a base substrate(700) with a micro component (702) attached thereto. Suitably it is provided with routing elements (704) for conducting signals to and from said component (702). It also comprises spacer members (706) which also can act as conducting structures for routing signals vertically. There is a capping structure (708) of a glass material, provided above the base substrate (700), bonded via said spacer members (706), preferably by eutectic bonding, wherein the capping structure (708) comprises vias (710) comprising metal for providing electrical connection through said capping structure. The vias can be made by a stamping/pressing method entailing pressing needles under heating to soften the glass and applying pressure, to a predetermined depth in the glass. However, other methods are possible, e-g- drilling, etching, blasting.
摘要翻译：一种装置包括具有附接到其上的微组件（702）的基底（700）。适当地，它设置有用于向组件（702）传导信号和从组件（702）传出信号的路由元件（704）。它还包括间隔件（706），其也可以用作垂直路线信号的导电结构。存在玻璃材料的覆盖结构（708），其设置在基底基板（700）上方，优选地通过共晶接合通过间隔件（706）接合，其中封盖结构（708）包括通孔（710），包括金属用于通过封盖结构提供电连接。通孔可以通过加压的冲压/压制方法制成，以使玻璃软化并施加压力至玻璃中的预定深度。然而，其他方法是可能的，例如钻孔，蚀刻，爆破。

59. 发明授权

EP1962679B1 METHODS FOR MAKING MICRO NEEDLES AND APPLICATIONS THEREOF 有权
标题翻译：用于生产微型针及其应用
公开(公告)号：EP1962679B1
公开(公告)日：2012-04-11
申请号：EP06824640.4
申请日：2006-12-14
申请人： Silex Microsystems AB
发明人： KÄLVESTEN, Edvard , EBEFORS, Thorbjörn , CORMAN, Thierry
IPC分类号： A61B5/042 , A61B5/151 , A61B5/153 , A61M25/06 , A61M37/00 , A61M5/158 , A61N1/18 , G01N33/483
CPC分类号： A61M37/0015 , A61B5/053 , A61B5/150022 , A61B5/150282 , A61B5/150984 , A61M2037/003 , A61M2037/0046 , A61M2037/0053 , A61N1/0502 , A61N1/0551 , H01L2224/48091 , H01L2224/8592 , H01L2924/00014
摘要： The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.

60. 发明授权

EP1987535B1 METHOD OF MAKING VIAS 有权
标题翻译：受理并联系
公开(公告)号：EP1987535B1
公开(公告)日：2011-06-01
申请号：EP07709445.6
申请日：2007-01-31
申请人： Silex Microsystems AB
发明人： KÄLVESTEN, Edvard , BAUER, Tomas , EBEFORS, Thorbjörn
IPC分类号： H01L21/768 , H01L23/48 , H01L23/522
CPC分类号： H01L23/49827 , H01L21/76898 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

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