专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

2. 发明授权

US09613863B2 Method for forming electroless metal through via 有权
公开(公告)号：US09613863B2
公开(公告)日：2017-04-04
申请号：US15040148
申请日：2016-02-10
申请人： SILEX MICROSYSTEMS AB
发明人： Thorbjorn Ebefors , Henrik Knutsson
IPC分类号： H01L21/44 , H01L21/768 , H01L21/288 , H01L23/48 , H01L21/02
CPC分类号： H01L21/76897 , H01L21/0217 , H01L21/02381 , H01L21/02532 , H01L21/02595 , H01L21/288 , H01L21/76847 , H01L21/76874 , H01L21/76879 , H01L21/76888 , H01L21/76892 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings

3. 发明申请

US20160122180A1 METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A FUNCTIONAL CAPPING 有权
标题翻译：制造具有功能性封盖的半导体器件的方法
公开(公告)号：US20160122180A1
公开(公告)日：2016-05-05
申请号：US14993714
申请日：2016-01-12
申请人： Silex Microsystems AB
发明人： Thorbjom Ebefors , Edvard Kalvesten , Tomas Bauer
IPC分类号： B81B7/00 , H01L23/498 , H01L23/66 , H01L23/04 , H01L23/64
CPC分类号： H01L21/50 , B81B7/007 , B81B2207/095 , B81C1/00301 , H01L21/6835 , H01L21/76898 , H01L21/78 , H01L23/04 , H01L23/10 , H01L23/481 , H01L23/49827 , H01L23/49838 , H01L23/552 , H01L23/585 , H01L23/642 , H01L23/645 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/81 , H01L24/83 , H01L2221/68363 , H01L2221/68372 , H01L2223/6616 , H01L2223/6622 , H01L2223/6655 , H01L2223/6677 , H01L2224/02311 , H01L2224/02313 , H01L2224/02371 , H01L2224/02372 , H01L2224/0239 , H01L2224/03462 , H01L2224/0401 , H01L2224/05073 , H01L2224/05155 , H01L2224/05548 , H01L2224/05573 , H01L2224/05644 , H01L2224/1146 , H01L2224/13009 , H01L2224/13024 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13155 , H01L2224/29009 , H01L2224/29011 , H01L2224/29012 , H01L2224/29018 , H01L2224/29101 , H01L2224/29111 , H01L2224/29144 , H01L2224/30051 , H01L2224/3012 , H01L2224/81005 , H01L2224/81203 , H01L2224/81801 , H01L2224/83005 , H01L2224/83203 , H01L2224/83801 , H01L2224/83805 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01072 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/01027 , H01L2924/01028 , H01L2924/3512
摘要： A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.
摘要翻译：一种制造微电子和/或微机械装置的晶片级方法，其具有通过连接（通孔）的电晶片的封盖，包括以下步骤：提供具有第一和第二侧面的半导体材料的第一晶片，以及第一侧中的多个孔和/或凹部，以及在第二侧上延伸到晶片上方的阻挡结构，所述屏障包括绝缘材料（例如氧化物）和另一材料的外层的内层。然后，将金属施加在所述孔中，以覆盖孔中的壁和孔的底部。去除阻挡结构，并且通过晶片背面上的连接将接触提供给晶片。粘合结构设置在晶片的所述第一侧或第二侧中的任一个上。晶片被接合到另一个承载电子和微电子/机械部件的晶片，使得第一晶片形成覆盖第二晶片的封盖结构。最后，将晶片单个化为单个器件。

4. 发明申请

US20150076677A1 CTE MATCHED INTERPOSER AND METHOD OF MAKING 有权
标题翻译： CTE匹配插件及其制作方法
公开(公告)号：US20150076677A1
公开(公告)日：2015-03-19
申请号：US14391855
申请日：2013-04-15
申请人： SILEX MICROSYSTEMS AB
发明人： Thorbjorn Ebefors , Daniel Perttu
IPC分类号： H01L23/498 , H01L23/31 , H01L21/48
CPC分类号： H01L23/49838 , H01L21/486 , H01L23/147 , H01L23/3142 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L2224/16 , H01L2924/1461 , H01L2924/00
摘要： The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter,
摘要翻译：本插入器使得可以在非常宽的范围内调整插入件的热膨胀系数以使其附着的部件相匹配。半导体插入器包括具有第一侧和相对的第二侧的半导体材料的衬底。至少有一个导电晶圆通孔包括金属。至少一个凹部设置在衬底的第一侧中，并且在衬底的半导体材料中，凹槽填充有金属并与晶片通孔连接，从而提供布线结构。金属填充的通孔和金属填充的凹部的暴露表面基本上与衬底的第一侧上的衬底表面齐平。晶圆通孔包括窄部分和较宽部分，并且接触元件设置在具有纵横比，高度：直径，<1：1，优选1：1至2：1的布线结构上。

5. 发明申请

US20150054136A1 METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE 有权
标题翻译：提供通孔和路由结构的方法
公开(公告)号：US20150054136A1
公开(公告)日：2015-02-26
申请号：US14389592
申请日：2013-03-28
申请人： SILEX MICROSYSTEMS AB
发明人： Thorbjorn Ebefors , Daniel Perttu
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76831 , H01L21/2885 , H01L21/76807 , H01L21/7684 , H01L21/76871 , H01L21/76879 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is
摘要翻译：提供通孔和布线结构的方法包括：提供具有设置在晶片表面上的凹陷和盲孔的衬底晶片; 在凹槽和孔中提供绝缘层; 对孔和凹槽进行金属化; 并且去除孔的底部中的氧化物层以提供晶片的背侧和前侧之间的接触。一种半导体器件，包括具有延伸穿过衬底的至少一个金属化通孔的衬底和形成与通孔一起布线的至少一个金属化凹槽。前侧场和后侧场均有氧化层。凹槽和通孔中的金属至少在前侧与场上的氧化物齐平，由此提供平坦的前侧。半导体器件的厚度<300μm。

6. 发明申请

WO2014051511A3 ELECTROLESS METAL THROUGH SILICON VIA 审中-公开
公开(公告)号：WO2014051511A3
公开(公告)日：2014-04-03
申请号：PCT/SE2013/051124
申请日：2013-09-27
申请人： SILEX MICROSYSTEMS AB
发明人： EBEFORS, Thorbjörn , KNUTSSON, Henrik
IPC分类号： H01L21/768 , H01L23/48 , H01L23/52
摘要： The invention relates to methods of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface. It comprises providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The the poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited Cu on the Ni by a plating process. Line widths and spacings

7. 发明申请

WO2013147694A1 METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE 审中-公开
标题翻译：提供通孔和路由结构的方法
公开(公告)号：WO2013147694A1
公开(公告)日：2013-10-03
申请号：PCT/SE2013/050353
申请日：2013-03-28
申请人： SILEX MICROSYSTEMS AB
发明人： EBEFORS, Thorbjörn , PERTTU, Daniel
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/2885 , H01L21/76807 , H01L21/7684 , H01L21/76871 , H01L21/76879 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method of providing a via hole and routing structure. A a substrate wafer having recesses and blind holes provided in the surface of the wafer is provided. An insulating layer is provided in the recesses and the holes, and the holes and recesses are metallized. The oxide layer in the bottom of the holes is removed to provide a contact between the back side and the front side of the wafer. The invention also provides a semiconductor device, comprising a substrate having at least one metallized via (V) extending through the substrate and at least one metallized recess forming a routing (RDL) together with the via (V). There is an oxide layer (ISO) on the front side field and on the back side field. The metal in the recess (RDL) and the via (V) is flush with the oxide (ISO) on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is
摘要翻译：本发明涉及一种提供通孔和布线结构的方法。提供了具有设置在晶片表面上的凹陷和盲孔的衬底晶片。在凹部和孔中设置有绝缘层，并且孔和凹槽被金属化。去除孔的底部中的氧化物层，以提供晶片的背侧和前侧之间的接触。本发明还提供了一种半导体器件，其包括具有延伸穿过衬底的至少一个金属化通孔（V）的衬底和与通孔（V）一起形成路由（RDL）的至少一个金属化凹槽。前侧场和背面场都有氧化层（ISO）。凹槽（RDL）和通孔（V）中的金属至少在前侧与场上的氧化物（ISO）齐平，由此提供平坦的前侧。半导体器件的厚度<300μm。

8. 发明申请

WO2010074649A1 VIA STRUCTURE AND METHOD THEREOF 审中-公开
标题翻译：通过其结构和方法
公开(公告)号：WO2010074649A1
公开(公告)日：2010-07-01
申请号：PCT/SE2009/051496
申请日：2009-12-23
申请人： SILEX MICROSYSTEMS AB , EBEFORS, Thorbjörn , KÄLVESTEN, Edvard , ÅGREN, Peter , SVEDIN, Niklas
发明人： EBEFORS, Thorbjörn , KÄLVESTEN, Edvard , ÅGREN, Peter , SVEDIN, Niklas
IPC分类号： H01L23/522 , B61B7/00 , B81C1/00 , H01L21/768 , G02B26/08
CPC分类号： G02B26/0833 , B81B7/0006 , B81B7/007 , B81B2207/092 , B81B2207/095 , G02B6/3518 , G02B6/3584 , G02B26/0841 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： The invention relates to a layered micro-electronic and/or micro-mechanic structure, comprising at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.
摘要翻译：本发明涉及分层的微电子和/或微机械结构，其包括在导电层之间具有绝缘层的至少三个交替的导电层。还提供了在第一外层中的通孔，所述通孔包括由穿过该层的晶片天然材料制成的绝缘导电连接，在第一外层中延伸穿过其它层并进入所述通孔的导电插塞，以便提供通过层的导电性，以及围绕所述其它层的至少一个所选层的所述导电插塞的绝缘外壳，用于使所述插塞与所述选定层中的材料绝缘。它还涉及微电子和/或微机械装置，其包括设置在空腔上方的可动构件，使得其可在至少一个方向上移动。该装置具有根据本发明的分层结构。还提供了制造这种分层MEMS结构的方法。

9. 发明申请

WO2010059118A1 FUNCTIONAL CAPPING 审中-公开
标题翻译：功能开机
公开(公告)号：WO2010059118A1
公开(公告)日：2010-05-27
申请号：PCT/SE2009/051311
申请日：2009-11-19
申请人： SILEX MICROSYSTEMS AB , EBEFORS, Thorbjörn , KÄLVESTEN, Edvard , BAUER, Thomas
发明人： EBEFORS, Thorbjörn , KÄLVESTEN, Edvard , BAUER, Thomas
IPC分类号： B81C1/00 , B81B7/00 , H01L21/50 , H01L23/48
CPC分类号： H01L21/50 , B81B7/007 , B81B2207/095 , B81C1/00301 , H01L21/6835 , H01L21/76898 , H01L21/78 , H01L23/04 , H01L23/10 , H01L23/481 , H01L23/49827 , H01L23/49838 , H01L23/552 , H01L23/585 , H01L23/642 , H01L23/645 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/81 , H01L24/83 , H01L2221/68363 , H01L2221/68372 , H01L2223/6616 , H01L2223/6622 , H01L2223/6655 , H01L2223/6677 , H01L2224/02311 , H01L2224/02313 , H01L2224/02371 , H01L2224/02372 , H01L2224/0239 , H01L2224/03462 , H01L2224/0401 , H01L2224/05073 , H01L2224/05155 , H01L2224/05548 , H01L2224/05573 , H01L2224/05644 , H01L2224/1146 , H01L2224/13009 , H01L2224/13024 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13155 , H01L2224/29009 , H01L2224/29011 , H01L2224/29012 , H01L2224/29018 , H01L2224/29101 , H01L2224/29111 , H01L2224/29144 , H01L2224/30051 , H01L2224/3012 , H01L2224/81005 , H01L2224/81203 , H01L2224/81801 , H01L2224/83005 , H01L2224/83203 , H01L2224/83801 , H01L2224/83805 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01072 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/01027 , H01L2924/01028 , H01L2924/3512
摘要： A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.
摘要翻译：一种制造微电子和/或微机械装置的晶片级方法，其具有通过连接（通孔）的电晶片的封盖，包括以下步骤：提供具有第一和第二侧的半导体材料的第一晶片，以及第一侧中的多个孔和/或凹部，以及在第二侧上延伸到晶片上方的阻挡结构，所述屏障包括绝缘材料（例如氧化物）和另一材料的外层的内层。然后，将金属施加在所述孔中，以覆盖孔中的壁和孔的底部。去除阻挡结构，并且通过晶片背面上的连接将接触提供给晶片。粘合结构设置在晶片的所述第一侧或第二侧中的任一个上。晶片接合到承载电子和微电子/机械部件的另一个晶片，使得第一晶片形成覆盖第二晶片的封盖结构。最后，将晶片单个化为单个器件。

10. 发明授权

US09511999B2 Thin film capping 有权
标题翻译：薄膜封盖
公开(公告)号：US09511999B2
公开(公告)日：2016-12-06
申请号：US14365235
申请日：2012-12-17
申请人： SILEX MICROSYSTEMS AB
发明人： Thorbjorn Ebefors , Niklas Svedin
IPC分类号： H01L21/76 , B81C1/00 , B81B7/00
CPC分类号： B81C1/00285 , B81B7/0038 , B81C1/00293 , B81C2203/0136 , B81C2203/0145
摘要： A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.
摘要翻译：一种用于在微电子/机械系统（MEMS）装置中密封空腔以在密封空腔内提供受控气氛的方法包括提供其上在基板的局部区域上提供模板的半导体衬底。模板定义了腔的内部形状。孔被制成以便能够排出空腔以提供期望的气氛以通过孔进入空腔。最后，在孔中设置密封材料以密封空腔。密封可以通过密封材料的压缩和/或熔化来制造。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式