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51. 发明授权

US09575754B2 Zero cycle move 有权
标题翻译：零循环移动
公开(公告)号：US09575754B2
公开(公告)日：2017-02-21
申请号：US13447651
申请日：2012-04-16
申请人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
发明人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/30032 , G06F9/384
摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.
摘要翻译：一种用于减少数据移动操作的延迟的系统和方法。处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。

52. 发明授权

US09430243B2 Optimizing register initialization operations 有权
标题翻译：优化寄存器初始化操作
公开(公告)号：US09430243B2
公开(公告)日：2016-08-30
申请号：US13460268
申请日：2012-04-30
申请人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III
发明人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3832 , G06F9/3857
摘要： A system and method for efficiently reducing the latency of initializing registers. A register rename unit within a processor determines whether prior to an execution pipeline stage it is known a decoded given instruction writes a particular numerical value in a destination operand. An example is a move immediate instruction that writes a value of 0 in its destination operand. Other examples may also qualify. If the determination is made, a given physical register identifier is assigned to the destination operand, wherein the given physical register identifier is associated with the particular numerical value, but it is not associated with an actual physical register in a physical register file. The given instruction is marked to prevent it from proceeding to an execution pipeline stage. When the given physical register identifier is used to read the physical register file, no actual physical register is accessed.
摘要翻译：一种用于有效减少初始化寄存器的延迟的系统和方法。处理器内的寄存器重命名单元确定在执行流水线阶段之前是否已知解码的给定指令将目标操作数中的特定数值写入。一个示例是在其目标操作数中写入值0的移动即时指令。其他示例也可能符合条件。如果确定，给定的物理寄存器标识符被分配给目的地操作数，其中给定的物理寄存器标识符与特定数值相关联，但是它不与物理寄存器文件中的实际物理寄存器相关联。给定的指令被标记为防止它进入执行流水线阶段。当给定的物理寄存器标识符用于读取物理寄存器文件时，不会访问实际的物理寄存器。

53. 发明授权

US09201658B2 Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries 有权
标题翻译：分支预测器，可以跨越高速缓存行边界进行广泛问题，任意对齐的提取
公开(公告)号：US09201658B2
公开(公告)日：2015-12-01
申请号：US13625382
申请日：2012-09-24
申请人： Ian D. Kountanis , Gerard R. Williams, III , James B. Keller
发明人： Ian D. Kountanis , Gerard R. Williams, III , James B. Keller
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3005 , G06F9/30058 , G06F9/38 , G06F9/3844 , G06F9/3848
摘要： In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, branch prediction values from multiple entries in each table may be read and respective branch prediction values may be combined to form branch predictions for up to M branches in the fetch group.
摘要翻译：在一个实施例中，处理器可以被配置为从指令高速缓存（“取出组”）获取N个指令字节，即使获取组跨越高速缓存行边界。分支预测器可以被配置为在获取组中产生多达M个分支的分支预测，其中M是可以包括在获取组中的最大分支数。在一个实施例中，可以读取每个表中来自多个条目的分支预测值，并且可以将相应的分支预测值组合以形成在取出组中多达M个分支的分支预测。

54. 发明授权

US08848577B2 Bandwidth management 有权
标题翻译：带宽管理
公开(公告)号：US08848577B2
公开(公告)日：2014-09-30
申请号：US13625416
申请日：2012-09-24
申请人： Gurjeet S. Saund , James B. Keller , Manu Gulati , Sukalpa Biswas
发明人： Gurjeet S. Saund , James B. Keller , Manu Gulati , Sukalpa Biswas
IPC分类号： H04L12/28
CPC分类号： G06F13/1605 , Y02D10/14
摘要： In some embodiments, a system includes a shared, high bandwidth resource (e.g. a memory system), multiple agents configured to communicate with the shared resource, and a communication fabric coupling the multiple agents to the shared resource. The communication fabric may be equipped with limiters configured to limit bandwidth from the various agents based on one or more performance metrics measured with respect to the shared, high bandwidth resource. For example, the performance metrics may include one or more of latency, number of outstanding transactions, resource utilization, etc. The limiters may dynamically modify their limit configurations based on the performance metrics. In an embodiment, the system may include multiple thresholds for the performance metrics, and exceeding a given threshold may include modifying the limiters in the communication fabric. There may be hysteresis implemented in the system as well in some embodiments, to reduce the frequency of transitions between configurations.
摘要翻译：在一些实施例中，系统包括共享的高带宽资源（例如，存储器系统），被配置为与共享资源通信的多个代理以及将多个代理耦合到共享资源的通信结构。通信结构可以配备有限制器，其被配置为基于针对共享的高带宽资源测量的一个或多个性能度量来限制来自各种代理的带宽。例如，性能度量可以包括延迟，未决事务数量，资源利用等中的一个或多个。限制器可以基于性能度量动态修改其限制配置。在一个实施例中，系统可以包括用于性能度量的多个阈值，并且超过给定阈值可以包括修改通信结构中的限制器。在一些实施例中，也可能在系统中实现滞后，以减少配置之间的转换频率。

55. 发明授权

US08359414B2 Retry mechanism 有权
标题翻译：重试机制
公开(公告)号：US08359414B2
公开(公告)日：2013-01-22
申请号：US13165235
申请日：2011-06-21
申请人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
发明人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F3/00 , G06F15/167
CPC分类号： G06F12/0831 , G06F13/362 , G06F13/4213 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.
摘要翻译：接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。在一个实施例中，控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。控制单元被配置为记录在互连上提供的标识符，该重试响应标识互连上正在进行的第二事务。控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。在另一个实施例中，控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应。控制单元还被配置为提供具有重试响应的第二事务的标识符。

56. 发明授权

US08219758B2 Block-based non-transparent cache 有权
标题翻译：基于块的不透明缓存
公开(公告)号：US08219758B2
公开(公告)日：2012-07-10
申请号：US12500810
申请日：2009-07-10
申请人： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
发明人： James Wang , Zongjian Chen , James B. Keller , Timothy J. Millet
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0802 , G06F12/0223 , G06F12/08 , G06F2212/2515 , Y02D10/13
摘要： In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.
摘要翻译：在一个实施例中，提供了一种非透明存储器单元，其包括非透明存储器和控制电路。控制电路可以将非透明存储器作为一组非透明存储器块进行管理。在一个或多个处理器上执行的软件可以请求处理数据的非透明存储器块。控制电路可以分配第一块，并且可以返回所分配的块的地址（或其他指示），使得软件可以访问块。控制电路还可以在非透明存储器与非透明存储器单元耦合到的主存储器系统之间提供自动数据移动。例如，自动数据移动可以包括在分配的块的处理完成之后从主存储器系统填充数据到所分配的块，或者将分配的块中的数据刷新到主存储器系统。

57. 发明授权

US08171326B2 L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down 有权
标题翻译： L1冲洗机构刷新缓存以断电并处理冲水和/或断电后的一致性
公开(公告)号：US08171326B2
公开(公告)日：2012-05-01
申请号：US12785842
申请日：2010-05-24
申请人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
发明人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
摘要翻译：在一个实施例中，处理器包括被配置为存储多个高速缓存块的数据高速缓存和耦合到数据高速缓存的控制单元。控制单元被配置为响应于处理器将转换到其中禁止用于处理器的一个或多个时钟的低功率状态的指示，从数据高速缓冲存储器中刷新多个高速缓存块。

58. 发明授权

US08086915B2 Memory controller with loopback test interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US08086915B2
公开(公告)日：2011-12-27
申请号：US12909073
申请日：2010-10-21
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G01R31/28 , G11C29/00 , G06F11/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

59. 发明申请

US20110035560A1 Memory Controller with Loopback Test Interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US20110035560A1
公开(公告)日：2011-02-10
申请号：US12909073
申请日：2010-10-21
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

60. 发明申请

US20110035518A1 Digital Phase Relationship Lock Loop 有权
标题翻译：数字相位锁定环路
公开(公告)号：US20110035518A1
公开(公告)日：2011-02-10
申请号：US12908605
申请日：2010-10-20
申请人： James Wang , Zongjian Chen , James B. Keller
发明人： James Wang , Zongjian Chen , James B. Keller
IPC分类号： G06F5/00
CPC分类号： G06F5/14
摘要： In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.
摘要翻译：在一个实施例中，一种装置包括可在对应于第一时钟信号的第一时钟域中操作的第一时钟存储装置。第一时钟存储设备具有耦合以接收从对应于第二时钟信号的第二时钟域在输入上发送的一个或多个位的输入。该装置还包括控制电路，其被配置为确保在输入上传输的一个或多个位的值的变化满足第一时钟存储设备的建立和保持时间要求。控制电路响应于第一时钟信号或第二时钟信号之一的采样历史，以在每个时钟周期上检测第一时钟信号和第二时钟信号之间的相位关系，以确保改变满足建立和保持时间要求。

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