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51. 发明授权

US07825472B2 Semiconductor device having a plurality of stacked transistors and method of fabricating the same 有权
标题翻译：具有多个堆叠晶体管的半导体器件及其制造方法
公开(公告)号：US07825472B2
公开(公告)日：2010-11-02
申请号：US12219278
申请日：2008-07-18
申请人： Han-Byung Park , Soon-Moon Jung , Hoon Lim , Cha-Dong Yeo , Byoung-Keun Son , Jae-Joo Shim , Chang-Min Hong
发明人： Han-Byung Park , Soon-Moon Jung , Hoon Lim , Cha-Dong Yeo , Byoung-Keun Son , Jae-Joo Shim , Chang-Min Hong
IPC分类号： H01L27/12
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/1108 , H01L27/1207
摘要： A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.
摘要翻译：根据示例性实施例的半导体器件可以具有多个堆叠的晶体管。半导体器件可以具有形成在半导体衬底上的下绝缘层和形成在下绝缘层上的上沟道体图案。源极区域和漏极区域可以形成在上部通道主体图案内，并且非金属转移栅极电极可以设置在源极和漏极区域之间的上部通道主体图案上。非金属转移栅电极，上通道体图案和下绝缘层可以被中间绝缘层覆盖。金属字线可以设置在中间绝缘层内以接触非金属转移栅电极的至少上表面。绝缘间隔物可以设置在金属字线的侧壁上。金属节点插头可以设置在中间绝缘层和下绝缘层内以接触上通道主体图案的源区域。示例性实施例还涉及制造上述半导体器件的方法。

52. 发明授权

US07777272B2 Non-volatile memory device and semiconductor package including the same 失效
标题翻译：非易失性存储器件和包括其的半导体封装
公开(公告)号：US07777272B2
公开(公告)日：2010-08-17
申请号：US12112965
申请日：2008-04-30
申请人： Sun-Pil Youn , Hyeong-Jun Kim , Jin-Tae Kang , Young-Jae Joo
发明人： Sun-Pil Youn , Hyeong-Jun Kim , Jin-Tae Kang , Young-Jae Joo
IPC分类号： H01L29/792 , H01L29/78 , H01L21/8247
CPC分类号： H01L29/7887 , H01L21/28273 , H01L21/28282 , H01L23/3128 , H01L25/0657 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/66833 , H01L29/7923 , H01L29/7926 , H01L2224/48227 , H01L2924/01019 , H01L2924/15311
摘要： A non-volatile memory device which can be highly-integrated without a decrease in reliability, and a method of fabricating the same, are provided. In the non-volatile memory device, a first doped layer of a first conductivity type is disposed on a substrate. A semiconductor pillar of a second conductivity type opposite to the first conductivity type extends upward from the first doped layer. A first control gate electrode substantially surrounds a first sidewall of the semiconductor pillar. A second control gate electrode substantially surrounds a second sidewall of the semiconductor pillar and is separated from the first control gate electrode. A second doped layer of the first conductivity type is disposed on the semiconductor pillar.
摘要翻译：提供了可以高度集成而不降低可靠性的非易失性存储器件及其制造方法。在非易失性存储器件中，第一导电类型的第一掺杂层设置在衬底上。与第一导电类型相反的第二导电类型的半导体柱从第一掺杂层向上延伸。第一控制栅电极基本上围绕半导体柱的第一侧壁。第二控制栅电极基本上围绕半导体柱的第二侧壁并与第一控制栅电极分离。第一导电类型的第二掺杂层设置在半导体柱上。

53. 发明授权

US07656696B2 Resistive memory device having resistor part for controlling switching window 有权
标题翻译：具有用于控制切换窗口的电阻部分的电阻式存储器件
公开(公告)号：US07656696B2
公开(公告)日：2010-02-02
申请号：US11353006
申请日：2006-02-14
申请人： Won Jae Joo , Kwang Hee Lee , Sang Kyun Lee , Yoon Sok Kang , Won Joo Kim
发明人： Won Jae Joo , Kwang Hee Lee , Sang Kyun Lee , Yoon Sok Kang , Won Joo Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C2213/31 , G11C2213/76 , H01L45/04 , H01L45/145
摘要： A resistive memory device having a resistor part for controlling a switching window. The resistive memory device of this disclosure can control a switching window to assure operational reliability thereof. In addition, since the memory device is realized by additionally providing only the resistor part for controlling a switching window to various resistive memory devices, it can be easily fabricated and applied to all current and voltage driving type resistive devices.
摘要翻译：一种具有用于控制切换窗口的电阻部分的电阻式存储器件。本公开的电阻式存储器件可以控制开关窗口以确保其操作可靠性。此外，由于通过额外仅设置用于控制到各种电阻式存储器件的开关窗口的电阻器部件来实现存储器件，因此可以容易地制造并施加到所有电流和电压驱动型电阻器件。

54. 发明申请

US20090286082A1 MONOMER FOR BINDING NANO-METAL, CONDUCTIVE POLYMER COMPOSITE AND METHOD OF PREPARING THE CONDUCTIVE POLYMER COMPOSITE 有权
标题翻译：用于结合纳米金属，导电聚合物复合材料的单体和制备导电聚合物复合材料的方法
公开(公告)号：US20090286082A1
公开(公告)日：2009-11-19
申请号：US12275745
申请日：2008-11-21
申请人： Byung Hee SOHN , Young Kwan LEE , Yi Yoiung YUN , Won Jae JOO
发明人： Byung Hee SOHN , Young Kwan LEE , Yi Yoiung YUN , Won Jae JOO
IPC分类号： B32B15/08 , C08G75/00 , B05D3/00
CPC分类号： C07D333/22 , H01B1/127 , H01B1/22 , Y10T428/294
摘要： Disclosed herein is a monomer for binding nano-metal, which is useful for the preparation of a conductor having increased conductivity with ensuring flexibility and transparency. Polymerization of the monomer for binding nano-metal provides a conductive polymer composite including a nano-metal rod. A method of preparing the conductive polymer composite is also provided.
摘要翻译：本文公开了用于结合纳米金属的单体，其可用于制备具有增加的导电性并且确保柔性和透明度的导体。用于结合纳米金属的单体的聚合提供了包括纳米金属棒的导电聚合物复合材料。还提供了制备导电聚合物复合材料的方法。

55. 发明申请

US20090273076A1 Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and elctronic apparatus including the same 有权
标题翻译：用于散热构件的胶带，包括散热构件的薄膜型半导体封装的芯片，以及包括该散热构件的电子装置
公开(公告)号：US20090273076A1
公开(公告)日：2009-11-05
申请号：US12385731
申请日：2009-04-17
申请人： Kyong-sei CHOI , Byung-seo Kim , Young-jae Joo , Ye-chung Chung , Kyong-soon Cho , Sang-heui Lee , Si-hoon Lee , Sa-yoon Kang , Dae-woo Son , Sang-gui Jo , Jeong-kyu Ha , Young-sang Cho
发明人： Kyong-sei CHOI , Byung-seo Kim , Young-jae Joo , Ye-chung Chung , Kyong-soon Cho , Sang-heui Lee , Si-hoon Lee , Sa-yoon Kang , Dae-woo Son , Sang-gui Jo , Jeong-kyu Ha , Young-sang Cho
IPC分类号： H01L23/498 , H01L23/36
CPC分类号： H01L23/49838 , H01L23/4985 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01079 , H05K1/0203 , H05K1/189 , H05K2201/09109 , H05K2201/1028 , H05K2201/10674 , H05K2203/1581 , H01L2924/00
摘要： Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.
摘要翻译：公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间绝缘基板的底表面和散热部件的顶表面。

56. 发明申请

US20080241559A1 Dendrimer having metallocene core, organic memory device using the same and manufacturing method thereof 有权
标题翻译：具有茂金属核的树枝状聚合物，使用其的有机记忆装置及其制造方法
公开(公告)号：US20080241559A1
公开(公告)日：2008-10-02
申请号：US11898979
申请日：2007-09-18
申请人： Won Jae Joo , Chulhee Kim , Kwang Hee Lee , Tae Lim Choi
发明人： Won Jae Joo , Chulhee Kim , Kwang Hee Lee , Tae Lim Choi
IPC分类号： B32B15/08 , B05D1/02 , B05D1/04 , C08F30/04 , B32B27/28 , B05D1/40
CPC分类号： G11C13/0014 , B82Y10/00 , C07F17/02 , C08G83/003 , G11C13/0009 , G11C13/0016 , H01L51/0083 , H01L51/0095 , H01L51/0591 , Y10T428/31663 , Y10T428/31678 , Y10T428/31688 , Y10T428/31855
摘要： Disclosed herein is a dendrimer, in which metallocene, which is an oxidation-reduction material, is located at a core, and a conjugated dendron is connected to the metallocene core by a linker compound, an organic active layer having the dendrimer, an organic memory device having the organic active layer and a method of manufacturing the organic active layer and the organic memory device. The organic memory device manufactured using a dendrimer having a metallocene core of example embodiments may have a shorter switching time, decreased operation voltage, decreased manufacturing cost and increased reliability, thereby realizing a highly-integrated large-capacity memory device.
摘要翻译：本文公开了一种树枝状大分子，其中作为氧化还原材料的茂金属位于核心，并且共轭树突通过连接体化合物连接到茂金属核，具有树枝状聚合物的有机活性层，有机记忆具有有机活性层的器件和制造有机活性层的方法和有机存储器件。使用具有示例性实施方案的茂金属核的树枝状聚合物制造的有机存储器件可以具有更短的开关时间，降低的操作电压，降低的制造成本和增加的可靠性，从而实现高度集成的大容量存储器件。

57. 发明申请

US20080094872A1 Method for forming organic layer pattern, organic layer pattern prepared by the same and organic memory devices comprising the pattern 失效
标题翻译：用于形成有机层图案的方法，由相同的有机层图案和包含图案的有机存储器件
公开(公告)号：US20080094872A1
公开(公告)日：2008-04-24
申请号：US11715956
申请日：2007-03-09
申请人： Sang Kyun Lee , Won Jae Joo , Kwang Hee Lee , Tae Lim Choi , Myung Sup Jung
发明人： Sang Kyun Lee , Won Jae Joo , Kwang Hee Lee , Tae Lim Choi , Myung Sup Jung
IPC分类号： G11C11/00 , B05D7/00 , C08F2/46
CPC分类号： H01L51/0018 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/51 , G11C2213/52 , H01L27/285
摘要： Disclosed are a method for forming an organic layer pattern which is characterized by forming a thin layer by coating a coating solution including a polyimide-based polymer having a heteroaromatic pendant group including a heteroatom in its polyimide major chain, a photoinitiator and a crosslinking agent on a substrate and drying the substrate, and exposing and developing the thin layer, an organic layer pattern prepared by the method, and an organic memory device comprising the pattern. According to example embodiments, a high-resolution micropattern may be formed without undergoing any expensive process, e.g., photoresist, leading to simplification of the preparation process and cost reduction.
摘要翻译：公开了一种形成有机层图案的方法，其特征在于通过在其聚酰亚胺主链中涂布包含具有包含杂原子的杂芳族侧基的聚酰亚胺基聚合物，光引发剂和交联剂的涂布溶液形成薄层，衬底并干燥衬底，以及曝光和显影薄层，通过该方法制备的有机层图案，以及包括图案的有机存储器件。根据示例实施例，可以形成高分辨率微图案，而不经历任何昂贵的工艺，例如光致抗蚀剂，导致制备过程的简化和成本降低。

58. 发明申请

US20070176189A1 Organic memory device and fabrication method thereof 有权
标题翻译：有机存储器件及其制造方法
公开(公告)号：US20070176189A1
公开(公告)日：2007-08-02
申请号：US11606888
申请日：2006-12-01
申请人： Won Jae Joo , Sang Kyun Lee
发明人： Won Jae Joo , Sang Kyun Lee
IPC分类号： H01L33/00 , H01L29/201
CPC分类号： H01L27/285 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/56 , G11C2213/77 , H01L51/0035 , H01L51/0036 , H01L51/0591
摘要： Disclosed herein are an organic memory device and a method for fabricating the device. The organic memory device may include a first electrode, a second electrode and an organic active layer wherein the organic active layer includes an upper organic material layer formed of an electrically conductive organic material containing heteroatoms and a lower organic material layer formed of an electrically non-conductive organic material containing heteroatoms. Because the organic memory device exhibits improved thermal stability and non-volatility, it may be well suited for use in nonvolatile large-capacity storage units. Flexible electrodes may be used in the organic memory device to fabricate flexible memory devices.
摘要翻译：本文公开了一种有机存储装置和用于制造该装置的方法。有机存储装置可以包括第一电极，第二电极和有机活性层，其中有机活性层包括由含有杂原子的导电有机材料形成的上部有机材料层和由非电解质形成的下部有机材料层，含有杂原子的导电有机材料。由于有机存储装置表现出改善的热稳定性和非挥发性，因此可能非常适用于非易失性大容量储存装置。可以在有机存储器件中使用柔性电极来制造柔性存储器件。

59. 发明申请

US20070075568A1 Package tray of vehicles and reinforcing structure thereof 失效
标题翻译：车辆包装托盘及其加固结构
公开(公告)号：US20070075568A1
公开(公告)日：2007-04-05
申请号：US11244259
申请日：2005-10-05
申请人： Ki Chang Kim , Jae Joo
发明人： Ki Chang Kim , Jae Joo
IPC分类号： B60J7/00
CPC分类号： B60R11/0217
摘要： A package tray of a vehicle includes a first reinforcing member installed to a woofer mount of a center panel and supported by a rear member and a second reinforcing member installed to the rear member to correspond to the woofer mount of the center panel in the front-to-rear direction. Thus, stiffness is increased so that noise, caused by vibration and/or tremble generated when a woofer outputs sound waves, can be minimized.
摘要翻译：车辆的包装托盘包括安装在中央面板的低音扬声器安装件上并由后部构件支撑的第一加强构件和安装在后部构件上的第二加强构件，以对应于前面的中央面板的低音扬声器支架，向后方向。因此，刚度增加，使得当低音扬声器输出声波时由振动和/或颤动引起的噪声可以被最小化。

60. 发明申请

US20060097319A1 Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby 有权
标题翻译：在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件
公开(公告)号：US20060097319A1
公开(公告)日：2006-05-11
申请号：US11197836
申请日：2005-08-05
申请人： Jong-Hyuk Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Sung-Jin Kim , Jae-Joo Shim
发明人： Jong-Hyuk Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Sung-Jin Kim , Jae-Joo Shim
IPC分类号： H01L27/01
CPC分类号： H01L21/8221 , H01L21/28525 , H01L21/76877 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/12 , H01L29/785
摘要： Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.
摘要翻译：提供了在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件。所述方法包括在单晶半导体层上形成层间绝缘层。形成单晶半导体插塞以穿透层间绝缘层。使用离子注入技术和退火技术在单晶半导体插头内形成半导体氧化物层。结果，单晶半导体插头被分成下插头和上部单晶半导体插头，半导体氧化物层之间插入其中。也就是说，上单晶半导体插头通过半导体氧化物层与下插塞电绝缘。单晶半导体图案形成为与上单晶半导体插头接触并覆盖层间绝缘层。通过使用上部单晶半导体插塞作为种子层的外延生长技术，或通过使用上部单晶半导体插塞作为种子层的固体外延生长技术，生长单晶半导体图案。

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