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51. 发明申请

US20160284729A1 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME 审中-公开
公开(公告)号：US20160284729A1
公开(公告)日：2016-09-29
申请号：US15176917
申请日：2016-06-08
申请人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
发明人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
IPC分类号： H01L27/115 , H01L23/528 , G11C16/10 , H01L23/522 , G11C16/04 , G11C16/26
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L23/5226 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

52. 发明授权

US09390803B2 Non-volatile memory devices, operating methods thereof and memory systems including the same 有权
公开(公告)号：US09390803B2
公开(公告)日：2016-07-12
申请号：US14849029
申请日：2015-09-09
申请人： Sun-il Shim , Jae-Hoon Jang , Donghyuk Chae , Youngho Lim , Hansoo Kim , Jaehun Jeong
发明人： Sun-il Shim , Jae-Hoon Jang , Donghyuk Chae , Youngho Lim , Hansoo Kim , Jaehun Jeong
IPC分类号： G11C16/10 , G11C16/12 , G11C16/04 , G11C16/34 , G11C16/08 , G11C16/14 , G11C16/26 , H01L27/115
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3418 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

53. 发明申请

US20120153014A1 PACKING BOX 有权
标题翻译：包装盒
公开(公告)号：US20120153014A1
公开(公告)日：2012-06-21
申请号：US13288186
申请日：2011-11-03
申请人： Jin Sik Won , Jung Il Shim
发明人： Jin Sik Won , Jung Il Shim
IPC分类号： B65D5/00
CPC分类号： B65D5/0254 , B65D5/10 , B65D5/6608 , B65D5/701 , Y10S206/807
摘要： A packing box includes a main body, an opening formed on one surface of the main body, left and right flaps extended from the left and right edges of the opening so as to cover the opening, a rear flap extended from the rear edge of the opening so as to be folded to the upper surfaces of the left and right flaps, an insertion flap extended from the front end of the rear flap so as to be inserted into an insertion hole, locking flaps extended from both sides of the insertion flap so as to maintain a closed state of the rear flap and unfolded to be supported by the left and right flaps after insertion of the locking flaps into the insertion hole, and fracture guide cutting lines formed at folded parts of the left and right flaps.
摘要翻译：包装箱包括主体，形成在主体的一个表面上的开口，从开口的左边缘和右边缘延伸的左右翼片以覆盖开口;后挡板，打开以便折叠到左右翼片的上表面，从后翼片的前端延伸的插入片插入到插入孔中，从插入片的两侧延伸的锁定片为了保持后挡板的关闭状态，并且在将锁定襟翼插入到插入孔中之后展开以被左右襟翼支撑，并且在左襟翼和右襟翼的折叠部分处形成断裂导向切割线。

54. 发明申请

US20120098048A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20120098048A1
公开(公告)日：2012-04-26
申请号：US13221380
申请日：2011-08-30
申请人： Byeong-In CHOE , Jae-Hoon JANG , Sun-Il SHIM , Han-Soo KIM , Jin-Man HAN
发明人： Byeong-In CHOE , Jae-Hoon JANG , Sun-Il SHIM , Han-Soo KIM , Jin-Man HAN
IPC分类号： H01L29/792 , H01L21/20
CPC分类号： H01L27/11582 , H01L29/7926
摘要： A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.
摘要翻译：垂直存储器件包括通道，接地选择线（GSL），字线和字符串选择线（SSL）。通道沿基本上垂直于基板的顶表面的第一方向延伸，并且通道的厚度根据高度而不同。 GSL，字线和SSL顺序地形成在通道的第一方向的侧壁上并且彼此间隔开。

55. 发明申请

US20110018036A1 VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：垂直非易失性存储器件及其制造方法
公开(公告)号：US20110018036A1
公开(公告)日：2011-01-27
申请号：US12636912
申请日：2009-12-14
申请人： Sung-min Hwang , Han-soo Kim , Won-seok CHO , Jae-hoon Jang , Sun-il Shim , Jae-hun Jeong , Ki-hyun Kim
发明人： Sung-min Hwang , Han-soo Kim , Won-seok CHO , Jae-hoon Jang , Sun-il Shim , Jae-hun Jeong , Ki-hyun Kim
IPC分类号： H01L27/085
CPC分类号： G11C5/06 , H01L23/5283 , H01L27/112 , H01L27/115 , H01L27/11517
摘要： A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.
摘要翻译：垂直非易失性存储器件被构造/制造成包括衬底，每组具有多个垂直分布的存储器晶体管的存储单元串组，使得衬底上多层的存储器，与存储器组合耦合的集成字线晶体管和字选择线的堆叠。每组的存储晶体管是一组存储单元串的晶体管，它们设置在衬底上方的相同层中。字选择线分别连接到集成字线。

56. 发明申请

US20080012015A1 METHOD FOR FABRICATING CuInS2 THIN FILM BY METAL ORGANIC CHEMICAL VAPOR DEPOSITION, CuInS2 THIN FILM FABRICATED BY THE SAME AND METHOD FOR FABRICATING In2S3 THIN FILM THEREFROM 失效
标题翻译：通过金属有机化学气相沉积法制备CuInS2薄膜的方法及其制备的CuInS2薄膜及其制备In2S3薄膜的方法
公开(公告)号：US20080012015A1
公开(公告)日：2008-01-17
申请号：US11775618
申请日：2007-07-10
申请人： Il SHIM , Seung LEE , Kook SEO , Jong PARK
发明人： Il SHIM , Seung LEE , Kook SEO , Jong PARK
IPC分类号： H01L29/24 , H01L21/36
CPC分类号： H01L31/0322 , C23C16/305 , Y02E10/541
摘要： Disclosed is a method for fabricating a CuInS2 thin film by metal-organic chemical vapor deposition (MOCVD). The method comprises fabricating a copper thin film by depositing an asymmetric copper precursor on a substrate by MOCVD and fabricating a CuInS2 thin film by depositing an indium-sulfur-containing precursor on the copper thin film by MOCVD. The method enables fabrication of a CuInS2 thin film with a constant composition even under vacuum as well as an argon (Ar) atmosphere. Disclosed is further a CuInS2 thin film fabricated by the method. Disclosed is further a method for fabricating an In2S3 thin film for a window of a solar cell via deposition of an indium-sulfur-containing precursor on the CuInS2 thin film by MOCVD. Disclosed further is an In2S3 thin film fabricated by the method. The In2S3 thin film is useful for a substitute for CdS conventionally used for windows of solar cells and contributes to simplification in fabrication process of solar cells.
摘要翻译：公开了通过金属有机化学气相沉积（MOCVD）制造CuInS 2 O 3薄膜的方法。该方法包括通过MOCVD在衬底上沉积不对称铜前体并通过MOCVD在铜薄膜上沉积含铟 - 硫的前体来制造CuInS 2＆lt; 2＆gt;薄膜来制造铜薄膜。该方法即使在真空以及氩（Ar）气氛下也能以恒定组成制造CuInS 2 N 2薄膜。还公开了通过该方法制造的CuInS 2 O 3薄膜。还公开了一种用于通过在CuInS 薄膜的方法 > 2 薄膜。还公开了通过该方法制造的In 2 N 3 S 3薄膜。 In 2＆lt; 3＆lt; 3＆gt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆lt; 3＆

57. 发明申请

US20070190690A1 Integrated circuit package system with exposed interconnects 有权
标题翻译：具有裸露互连的集成电路封装系统
公开(公告)号：US20070190690A1
公开(公告)日：2007-08-16
申请号：US11354806
申请日：2006-02-14
申请人： Seng Chow , Il Shim , Byung Han
发明人： Seng Chow , Il Shim , Byung Han
IPC分类号： H01L21/00 , H01L23/34
CPC分类号： H01L24/97 , H01L21/561 , H01L21/566 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2225/1088 , H01L2225/1094 , H01L2924/00014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01067 , H01L2924/01079 , H01L2924/01082 , H01L2924/07811 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2224/85 , H01L2224/83 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system is provided including providing a substrate having a first surface and second surface; mounting interconnects to the first surface; mounting integrated circuit dies to the first surface; embedding the interconnects and the integrated circuit die within an encapsulant on the substrate and leaving top portions of the interconnects exposed; attaching solder balls to the second surface; and singulating the substrate and the encapsulant into a plurality of integrated circuit packages.
摘要翻译：提供一种集成电路封装系统，包括提供具有第一表面和第二表面的衬底; 将互连件安装到第一表面; 将集成电路模具安装到第一表面; 将所述互连和所述集成电路管芯嵌入在所述衬底上的密封剂中并且使所述互连的顶部部分暴露; 将焊球附接到第二表面; 以及将所述衬底和所述密封剂分离成多个集成电路封装。

58. 发明申请

US20060043559A1 Stacked die packaging and fabrication method 有权
公开(公告)号：US20060043559A1
公开(公告)日：2006-03-02
申请号：US10931919
申请日：2004-08-31
申请人： Seng Chow , Ming Ying , Il Shim , Roger Emigh
发明人： Seng Chow , Ming Ying , Il Shim , Roger Emigh
IPC分类号： H01L23/02
CPC分类号： H01L25/50 , H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2924/00014 , H01L2924/01079 , H01L2924/181 , H01L2924/19041 , H01L2924/19103 , H01L2924/19105 , H01L2924/30107 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a substrate. A crenellated spacer is attached to the substrate. At least one top die is attached to the crenellated spacer. The at least one top die is wire bonded to the substrate, and an encapsulant is formed over the crenellated spacer and the at least one top die.

59. 发明申请

US20050161780A1 Strip-fabricated flip chip in package and flip chip in system heat spreader assemblies and fabrication methods therefor 有权
标题翻译：带式制造的倒装芯片封装和倒装芯片系统散热器组件及其制造方法
公开(公告)号：US20050161780A1
公开(公告)日：2005-07-28
申请号：US10766746
申请日：2004-01-27
申请人： Tie Wang , Virgil Ararao , Il Shim , Sheila Marie Alvarez
发明人： Tie Wang , Virgil Ararao , Il Shim , Sheila Marie Alvarez
IPC分类号： H01L21/44 , H01L23/02 , H01L23/31 , H01L23/433
CPC分类号： H01L23/3128 , H01L23/4334 , H01L24/97 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/97 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2224/81 , H01L2924/00
摘要： A method for fabricating a semiconductor package with a substrate in a strip format is provided. Semiconductor devices are attached in a strip format to the substrate, and a thermal interface material is applied to the semiconductor devices. A flat panel heat spreader is attached to each semiconductor device. The semiconductor devices are encapsulated with open encapsulation, leaving the surface of the flat panel heat spreader opposite the substrate externally exposed. Individual semiconductor packages are then singulated from the strip format.
摘要翻译：提供了一种以条形格式制造具有衬底的半导体封装的方法。半导体器件以条形格式附接到衬底，并且热界面材料被施加到半导体器件。平板式散热器安装在每个半导体器件上。半导体器件用开放封装封装，使平板散热器的表面与外部裸露的衬底相对。然后单独的半导体封装从条形格式分割。

60. 发明申请

US20050142667A1 Fabrication method of self-aligned ferroelectric gate transistor using buffer layer of high etching selectivity 有权
标题翻译：使用高蚀刻选择性的缓冲层的自对准铁电栅极晶体管的制造方法
公开(公告)号：US20050142667A1
公开(公告)日：2005-06-30
申请号：US10922949
申请日：2004-08-23
申请人： Yong-Tae Kim , Seong-Il Kim , Chun-Keun Kim , Sun-Il Shim
发明人： Yong-Tae Kim , Seong-Il Kim , Chun-Keun Kim , Sun-Il Shim
IPC分类号： H01L21/3065 , H01L21/00 , H01L21/265 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8246 , H01L27/105 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6684 , H01L21/2652 , H01L21/28291 , H01L29/66575
摘要： A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectric layer, and etching is performed on a portion where a source and a drain will be formed and then stopped at the buffer layer, thereby fabricating a self-aligned ferroelectric gate transistor without damage to the silicon thin film, and thus, an integration degree of a chip can be improved.
摘要翻译：公开了使用具有高蚀刻选择性的缓冲层的自对准铁电栅极晶体管的制造方法。在硅衬底和铁电体层之间形成具有高蚀刻选择性的缓冲层的堆叠结构，并且对形成源极和漏极的部分进行蚀刻，然后在缓冲层处停止，自对准的铁电栅极晶体管，而不损坏硅薄膜，从而可以提高芯片的集成度。

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