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    • 53. 发明授权
    • Multistaged amplification circuit
    • 多级放大电路
    • US06906589B2
    • 2005-06-14
    • US10605571
    • 2003-10-09
    • Takeshi IkedaHiroshi Miyagi
    • Takeshi IkedaHiroshi Miyagi
    • H03F1/26H03F1/32H03F3/45H03F3/68
    • H03F3/68H03F3/45183H03F2203/45051H03F2203/45652
    • A plurality of transistors Qi (i=1 to n), which are connected to a plurality of differential amplifiers 1, 2, and 3 and which are connected in a multistaged manner and connected to one constant current source 4 by a current mirror, are arranged collectively on an input side of the constant current source 4. Due to this, the wiring length between the constant current source 4 and the transistors Qi is shortened to the utmost, and the stability of circuit can be improved. Also, this can restrict the unfavorableness that noise is superposed on the wiring. Additionally, a voltage drop will not occur due to supplied resistance on the ground line, due to each transistor Qi being grounded to the same place via separate ground lines 6, 7, and 8. Because of this, the current can be supplied from the constant current source 4 to all transistors Qi without breaking the balance of the current mirror.
    • 连接到多个差分放大器1,2和3并且以多级方式连接并通过电流镜连接到一个恒流源4的多个晶体管Qi(i = 1至n)分别是 集中配置在恒流源4的输入侧。 由此,恒定电流源4与晶体管Qi之间的布线长度被最大限度地缩短,能够提高电路的稳定性。 此外,这可以限制噪声叠加在布线上的不利因素。 此外,由于每个晶体管Qi通过单独的接地线6,7和8接地到相同的地方,所以由于地线上的电阻而不会发生电压降。 因此,可以将电流从恒定电流源4提供给所有晶体管Qi而不破坏电流镜的平衡。
    • 54. 发明申请
    • Semiconductor integrated circuit for a radio apparatus and radio communication apparatus
    • 一种用于无线电设备和无线电通信装置的半导体集成电路
    • US20050122243A1
    • 2005-06-09
    • US10502833
    • 2003-02-03
    • Hiroshi MIYAGI
    • Hiroshi MIYAGI
    • H03J1/00H03J3/08H03J3/28H03J5/02H03M1/66H04B1/16H04B1/18H04B1/26H03M1/12
    • H04B1/16H03J1/0033H04B1/18
    • Adjustment data of first and second tracking adjustment circuits 11 and 12 are set in latch circuits 21 and 22. The plurality of pieces of adjustment data latched by the latch circuits 21 and 22 are respectively output to one D/A converter 41 at different time intervals. The data are converted into a direct current control voltage in the D/A converter 41, and the control voltage is respectively held by voltage holding circuits of the first tracking adjustment circuit 11 and the second tracking adjustment circuit 12, and a tuning frequency is adjusted. After an optimum tuning frequency is obtained, the tuning data at that time is written to a nonvolatile memory within an IC, and the control voltage is supplied to each tuning circuit based on the tuning data stored in the nonvolatile memory.
    • 第一和第二跟踪调整电路11和12的调整数据被设置在锁存电路21和22中。 由锁存电路21和22锁存的多个调节数据分别以不同的时间间隔输出到一个D / A转换器41。 数据被转换成D / A转换器41中的直流控制电压,并且控制电压分别由第一跟踪调整电路11和第二跟踪调整电路12的电压保持电路保持,调谐频率被调整 。 在获得最佳调谐频率之后,此时的调谐数据被写入到IC内的非易失性存储器中,并且基于存储在非易失性存储器中的调谐数据将控制电压提供给每个调谐电路。
    • 55. 发明申请
    • AUTOMATIC GAIN CONTROL CIRCUIT
    • 自动增益控制电路
    • US20050007192A1
    • 2005-01-13
    • US10494657
    • 2002-11-12
    • Hiroshi Miyagi
    • Hiroshi Miyagi
    • H03G3/30H03G1/00H03G3/20H04B1/16
    • H03G1/00
    • An automatic gain control circuit integrally fabricated on a semiconductor substrate. An AGC circuit 17 controls the gain of an intermediate-frequency amplifier circuit 15 so that the average level of the output signal (sound signal) of an AM detector circuit 16 may be substantially constant. The AGC circuit 17 includes a time-constant circuit 100, which comprises a charging circuit for intermittently charging the capacitor and a discharging circuit for intermittently discharging the same. By this intermittent charging and discharging of the capacitor having a small capacitance, a large time constant is set.
    • 一种整体制造在半导体衬底上的自动增益控制电路。 AGC电路17控制中频放大器电路15的增益,使得AM检测器电路16的输出信号(声音信号)的平均电平基本上是恒定的。 AGC电路17包括时间常数电路100,其包括用于间断地对电容器充电的充电电路和用于间歇地对电容器进行放电的放电电路。 通过对具有小电容的电容器进行间歇充放电,设定大的时间常数。
    • 56. 发明授权
    • Filter circuit
    • 滤波电路
    • US06744307B2
    • 2004-06-01
    • US10406186
    • 2003-04-04
    • Takeshi IkedaHiroshi Miyagi
    • Takeshi IkedaHiroshi Miyagi
    • H03K500
    • H03H11/04H03H11/1213
    • A filter includes a capacitor (1) connected between the input end IN and the output end OUT of signals and constant current circuits (2, 3) of MOS structure connected between the power source VDD and the ground, and by connecting the output side node of the capacitor (1) and the intermediate node of the constant current circuits (2, 3). Thus, the cut-off frequency of the filter is reduced dy adjusting the value of a current passed through the constant current circuits (2, 3), instead of increasing the circuit area required by using a capacitor having a large capacitance value or a resistor having a large resistance value.
    • 滤波器包括连接在电源VDD和地之间的MOS结构的信号和恒流电路(2,3)的输入端IN和输出端OUT之间的电容器(1),并且通过连接输出侧节点 的电容器(1)和恒流电路(2,3)的中间节点。 因此,通过调节通过恒流电路(2,3)的电流的值来减小滤波器的截止频率,而不是增加使用具有大电容值的电容器所需的电路面积或电阻 具有较大的电阻值。
    • 57. 发明申请
    • HARMONIC SUPPRESSING CIRCUIT
    • 谐波抑制电路
    • US20100219909A1
    • 2010-09-02
    • US12161653
    • 2006-09-21
    • Takashi IkedaHiroshi Miyagi
    • Takashi IkedaHiroshi Miyagi
    • H03H7/00
    • H03G9/00H03G9/08
    • There are included an LPF (3) and an HPF (4) that are connected in parallel to the output of a pre-emphasis circuit (2). There is also included a gain adjusting circuit (6) that performs a gain adjustment of low-pass filter with respect to the frequency band to be passed through the HPF (4). The low frequency components of the frequency band of baseband signals outputted from the pre-emphasis circuit (2) pass through the LPF (3), while the high frequency components pass through the HPF (4). As to the outputs from the HPF (4), the gain of especially the higher part of the frequency band components to be passed through the HPF (4) is suppressed by the gain adjusting circuit (6), whereby the amplitudes of the baseband signals can be limited only for the high frequency range without using a limiter and further the peak values of the baseband signals can be inhibited from exceeding the maximum frequency deviation.
    • 包括与预加重电路(2)的输出并联连接的LPF(3)和HPF(4)。 还包括增益调整电路(6),其对相对于通过HPF(4)的频带执行低通滤波器的增益调整。 从预加重电路(2)输出的基带信号的频带的低频分量通过LPF(3),而高频分量通过HPF(4)。 对于HPF(4)的输出,通过增益调整电路(6)抑制要通过HPF(4)的频带分量的较高部分的增益,从而基带信号的幅度 可以仅限于高频范围而不使用限制器,并且可以抑制基带信号的峰值超过最大频率偏差。
    • 58. 发明申请
    • ANTENNA INPUT TUNING CIRCUIT
    • 天线输入调谐电路
    • US20090253395A1
    • 2009-10-08
    • US12303157
    • 2007-02-06
    • Takeshi IkedaHiroshi Miyagi
    • Takeshi IkedaHiroshi Miyagi
    • H04B1/18
    • H04B1/18H03H11/1252H03H11/1291H03J2200/06H03J2200/10H03J2200/18H03L7/08H03L7/0805
    • There are provided a variable tuning filter 11 for selecting any of resistance elements by changing over a switch to cause a tuning frequency fF to be variable, and an oscillating circuit 12 constituted in the same manner as the variable tuning filter 11, and an oscillating frequency fL of the oscillating circuit 12 which is monitored by a frequency counter 13 and a desirable received frequency fr which is preset by a control circuit 14 are compared with each other based on respective frequency count values, and the oscillating frequency fL of the oscillating circuit 12 is varied in such a manner that both of the frequencies are coincident with each other within an allowable error range, and correspondingly, the tuning frequency fF of the variable tuning filter 11 is also varied. Consequently, it is possible to adjust the tuning frequency fF of the variable tuning filter 11 to be coincident with the desirable received frequency fr without using a variable capacitance diode which is hard to integrate or the like.
    • 提供了可变调谐滤波器11,用于通过切换开关来选择任何电阻元件,以使调谐频率fF可变,以及以与可变调谐滤波器11相同的方式构成的振荡电路12和振荡频率 由频率计数器13监视的振荡电路12的fL和由控制电路14预置的期望接收频率fr相互比较,并且振荡电路12的振荡频率fL 以允许误差范围内的两个频率彼此一致的方式变化,相应地,可变调谐滤波器11的调谐频率fF也变化。 因此,可以将可变调谐滤波器11的调谐频率fF调整为与期望的接收频率fr一致,而不使用难以集成的可变电容二极管等。
    • 59. 发明申请
    • RECEIVER
    • 接收器
    • US20090215422A1
    • 2009-08-27
    • US12393214
    • 2009-02-26
    • Takeshi IkedaHiroshi Miyagi
    • Takeshi IkedaHiroshi Miyagi
    • H04B1/16
    • H04B1/18H04B1/0007
    • By providing switch portions (8a) and (8b) for switching I and Q signals and outputting them to a single A/D converter (9), and sequentially converting the I and Q signals output from the switch portions (8a) and (8b) into digital signals by the A/D converter (9) and supplying them to a DSP (10), it is possible to carry out an A/D conversion processing for the I and Q signals through the same A/D converter (9). Consequently, it is possible to eliminate a drawback that an amplitude error or a phase error is made between the I and Q signals due to a variation in an A/D converting characteristic.
    • 通过提供用于切换I和Q信号并将其输出到单个A / D转换器(9)的开关部分(8a)和(8b),并且顺序地转换从开关部分(8a)和(8b)输出的I和Q信号 )由A / D转换器(9)转换为数字信号并将其提供给DSP(10),可以通过相同的A / D转换器(9)对I和Q信号执行A / D转换处理 )。 因此,可以消除由于A / D转换特性的变化而导致I和Q信号之间产生振幅误差或相位误差的缺点。