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51. 发明授权

US09805782B1 Memory device capable of determining candidate wordline for refresh and control method thereof 有权
公开(公告)号：US09805782B1
公开(公告)日：2017-10-31
申请号：US15422488
申请日：2017-02-02
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Jian-Sing Liou
IPC分类号： G11C7/00 , G11C11/403 , G11C11/408
CPC分类号： G11C11/403 , G11C11/40607 , G11C11/40615 , G11C11/4085 , G11C11/4087
摘要： A memory device includes an address generation circuit, an address processing circuit and a refresh control circuit. The address generation circuit generates a first intermediate address according to a row address. The first intermediate address includes a first wordline address and an identification code indicating whether a first wordline indicated by the first wordline address is a normal or redundant wordline. The address processing circuit refers to the first intermediate address to generate a second intermediate address indicating a second wordline adjacent to the first wordline. The second intermediate address includes a second wordline address and an identification code indicating whether the second wordline is a normal or redundant wordline. The refresh control circuit determines a disturbance count of the second wordline each time the first wordline is activated, and refers to the disturbance count to determine whether to output the second wordline address to refresh the second wordline.

52. 发明申请

US20170201220A1 VARIABLE GAIN AMPLIFYING CIRCUIT 有权
公开(公告)号：US20170201220A1
公开(公告)日：2017-07-13
申请号：US14990836
申请日：2016-01-08
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Szu-chun TSAO , Deng-Yao SHIH
IPC分类号： H03G3/30 , H03F3/45
CPC分类号： H03G3/30 , H03F1/12 , H03F3/45475 , H03F2203/45112 , H03F2203/45116 , H03F2203/45528 , H03F2203/45534 , H03G1/0023 , H03G1/0088
摘要： A variable gain amplifying circuit incorporates an operational amplifier, an input device, a feedback device, a transconductance circuit, and a dynamic biasing circuit. The operational amplifier has an output terminal providing an amplified difference output signal. The input device has a first terminal receiving a first input signal, and a second terminal coupled to a first input terminal of the operational amplifier. The feedback device is coupled between the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The dynamic biasing circuit generates a bias current to according to a set value. The transconductance circuit converts the difference between the first input signal and a second input signal into an analog output current flowing through the feedback device. The analog output current of the transconductance circuit is varied according to the bias current.

53. 发明申请

US20160308352A1 PROTECTION CIRCUIT FOR PREVENTING AN OVER-CURRENT FROM AN OUTPUT STAGE 有权
标题翻译：用于防止从输出阶段过流的保护电路
公开(公告)号：US20160308352A1
公开(公告)日：2016-10-20
申请号：US14685611
申请日：2015-04-14
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Szu-Chun Tsao
IPC分类号： H02H9/02
CPC分类号： H02H9/025 , H03K17/0822
摘要： A semiconductor device including: an output stage, including a PMOS, an NMOS and an output terminal, wherein a source terminal of the PMOS is connected to a first supply voltage, a drain terminal of the PMOS is connected to a drain terminal of the NMOS and the output terminal, a source terminal of the NMOS is connected to a second supply voltage, and the output terminal outputs an output signal; and a protection circuit, including a first voltage clamping circuit, including a first transistor, a second transistor and a first switch, wherein the first transistor and the second transistor are for clamping a gate voltage of the PMOS of the output stage and are connected in series, the first switch is coupled to the first supply voltage and a node between the first transistor and the second transistor for selectively coupling the first supply voltage to the node.
摘要翻译：一种半导体器件，包括：输出级，包括PMOS，NMOS和输出端，其中PMOS的源极端子连接到第一电源电压，PMOS的漏极端子连接到NMOS的漏极端子和所述输出端子，所述NMOS的源极端子连接到第二电源电压，并且所述输出端子输出输出信号; 以及包括第一电压钳位电路的保护电路，包括第一晶体管，第二晶体管和第一开关，其中第一晶体管和第二晶体管用于钳位输出级的PMOS的栅极电压，第一开关耦合到第一电源电压和第一晶体管和第二晶体管之间的节点，用于选择性地将第一电源电压耦合到节点。

54. 发明申请

US20150332769A1 METHOD FOR PROGRAMMING SELECTED MEMORY CELLS IN NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE THEREOF 有权
标题翻译：用于在非易失性存储器件中编程选择的存储器单元的方法及其非易失性存储器件
公开(公告)号：US20150332769A1
公开(公告)日：2015-11-19
申请号：US14280606
申请日：2014-05-17
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： CHUNG-SHAN KUO
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C13/0069 , G11C16/08 , G11C16/3418 , G11C16/3427 , G11C2013/0092
摘要： A method for programming memory cells of a selected word line has steps of: providing a first word line programming signal being at plurality of voltage levels in different programming slots of a current programming operation to the memory cells of the selected word line, wherein the first word line programming signal is a ramping voltage signal; and providing a second line programming signal being at plurality of voltage levels in different programming slots of a next programming operation to the memory cells of the selected word line, wherein the second word line programming signal is another one ramping voltage signal; wherein the highest voltage levels of the first and second word line programming signals are identical to each other, and a number of the voltage levels of the first word line programming signal is larger than that of the second word line programming signal.
摘要翻译：一种用于对所选字线的存储单元进行编程的方法包括以下步骤：将当前编程操作的不同编程时隙中的多个电压电平的第一字线编程信号提供给所选字线的存储单元，其中第一字线编程信号是斜坡电压信号; 以及向所述选定字线的存储单元提供在下一个编程操作的不同编程时隙中的多个电压电平的第二行编程信号，其中所述第二字线编程信号是另一个斜坡电压信号; 其中所述第一和第二字线编程信号的最高电压电平彼此相同，并且所述第一字线编程信号的电压电平的数量大于所述第二字线编程信号的电压电平的数量。

55. 发明授权

US09117546B2 Method for auto-refreshing memory cells in semiconductor memory device and semiconductor memory device using the method 有权
标题翻译：使用该方法自动刷新半导体存储器件和半导体存储器件中的存储单元的方法
公开(公告)号：US09117546B2
公开(公告)日：2015-08-25
申请号：US14032159
申请日：2013-09-19
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： Ming-Chien Huang
IPC分类号： G11C7/00 , G11C11/406 , G11C8/12 , G11C11/408
CPC分类号： G11C11/40618 , G11C8/12 , G11C11/40611 , G11C11/4087
摘要： An exemplary embodiment of the present disclosure illustrates a method for auto-refreshing memory cells in a semiconductor memory device with an open bit line architecture, wherein the semiconductor memory device comprises M memory banks, and each of the M memory banks has two particular sectors with a same index and L remained sectors with different indices. Two word lines of the two particular sectors with the same index in the memory bank and (M−1) word lines of the L remained sectors respectively in the other (M−1) memory banks are selected in one cycle. Then, memory cells of the selected word lines are refreshed.
摘要翻译：本公开的示例性实施例示出了用于利用开放位线架构自动刷新半导体存储器件中的存储器单元的方法，其中半导体存储器件包括M个存储体，并且M个存储器组中的每一个具有两个具有相同的指数和L仍然是不同指数的行业。在另一（M-1）个存储体中分别在存储体中具有相同索引的两个特定扇区的两个字线和分别位于其他（M-1）个存储体中的L个剩余扇区的（M-1）个字线在一个周期中选择。然后，刷新所选字线的存储单元。

56. 发明授权

US08995187B2 Nonvolatile semiconductor memory device programmable via overlapping pulse signals 有权
标题翻译：非易失性半导体存储器件可通过重叠脉冲信号编程
公开(公告)号：US08995187B2
公开(公告)日：2015-03-31
申请号：US13760969
申请日：2013-02-06
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Cheng-Hung Tsai
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/10
摘要： A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: dividing the plurality of memory cells into M number of groups (M is an integer); successively selecting each of the M number of groups; generating M number of successive overlapping pulse signals; and programming the memory cells of the M number of groups in response to the respective M number of successive overlapping pulse signals.
摘要翻译：一种用于编程非易失性半导体存储器件的多个存储器单元的方法包括以下步骤：将多个存储器单元划分成M个组（M是整数）; 依次选择M个组中的每一个; 产生M个连续的重叠脉冲信号; 以及响应于相应的M个连续的重叠脉冲信号来编程M个组的存储器单元。

57. 发明申请

US20150058613A1 METHOD OF BOOTING SYSTEM HAVING NON-VOLATILE MEMORY DEVICE WITH ERASE CHECKING AND CALIBRATION MECHANISM AND RELATED MEMORY DEVICE 有权
标题翻译：具有擦除检查和校准机制的非易失性存储器件的触摸系统的方法及相关的存储器件
公开(公告)号：US20150058613A1
公开(公告)日：2015-02-26
申请号：US14010475
申请日：2013-08-26
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Chung-Shan Kuo , Chih-Hao Chen
IPC分类号： G06F11/14
CPC分类号： G06F11/1441 , G11C7/1006 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/4076
摘要： A method of booting a system with a non-volatile memory device includes at least the following steps: when the system is powered on, reading a status flag of at least a memory block of the non-volatile memory device, wherein the status flag indicates whether an erase operation applied to the memory block is successfully completed; selectively performing a leakage calibration process upon the memory block according to the status flag; and booting the system according to a boot code stored in the non-volatile memory device.
摘要翻译：用非易失性存储器装置引导系统的方法至少包括以下步骤：当系统通电时，读取非易失性存储器件的至少存储块的状态标志，其中状态标志指示是否成功完成了应用于存储器块的擦除操作; 根据状态标志选择性地对存储器块执行泄漏校准处理; 以及根据存储在所述非易失性存储器设备中的引导代码引导所述系统。

58. 发明申请

US20150019927A1 TEST SYSTEM AND DEVICE 有权
标题翻译：测试系统和设备
公开(公告)号：US20150019927A1
公开(公告)日：2015-01-15
申请号：US14315127
申请日：2014-06-25
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Jen-Shou HSU , Po-Hsun WU
IPC分类号： G01R31/3177
CPC分类号： G01R31/2863 , G01R31/2868 , G01R31/2889
摘要： An aspect of the present invention is to provide a test system for detecting whether a continuity fault condition, e.g., a short or open condition, exists in the path between a tester and chips on a wafer during a wafer level burn-in testing. According to one embodiment of the present invention, the test system comprises a probe card and n chips. The probe card comprises m first signal contacts for receiving m test signals from the tester, n second signal contacts for providing n test results to the tester, and a contact array. The probe card is in contact with the chips on the wafer through a plurality of needles. In this manner, the test system can detect whether the continuity fault condition exists in the path between the tester and the chips on the wafer during the wafer level burn-in testing.
摘要翻译：本发明的一个方面是提供一种测试系统，用于在晶片级老化测试期间检测测试仪和晶片上的芯片之间的路径中是否存在连续性故障状况，例如短路或开路状态。根据本发明的一个实施例，测试系统包括探针卡和n个芯片。探针卡包括m个第一信号触点，用于从测试器接收m个测试信号，n个第二信号触点用于向测试器提供n个测试结果，以及一个触点阵列。探针卡通过多个针与晶片上的芯片接触。以这种方式，测试系统可以在晶片级老化测试期间检测测试仪和晶片上的芯片之间的路径中是否存在连续性故障条件。

59. 发明申请

US20140362654A1 REDUNDANCY EVALUATION CIRCUIT FOR SEMICONDUCTOR DEVICE 有权
标题翻译：用于半导体器件的冗余评估电路
公开(公告)号：US20140362654A1
公开(公告)日：2014-12-11
申请号：US13912827
申请日：2013-06-07
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： YA-CHUN LAI
IPC分类号： G11C29/04
CPC分类号： G11C29/027 , G11C29/785 , G11C29/787 , G11C29/80 , G11C29/806 , G11C2029/4402
摘要： A redundancy evaluation circuit has (m+1) fuse boxes and a comparator, wherein the m fuse box output a fuse status address signal and the other one fuse box outputs a comparator enable signal. Each fuse box has a common stage circuit and k redundant cells. The k redundant cells shares the precharge transistor and an inverted latch of the common stage circuit, and the fuse in the selected redundant cell affects the output of the corresponding fuse box. The comparator enabled by the comparator enable signal compares the fuse status address signal and a defective element address signal to generate a redundancy enable signal. The redundancy evaluation circuit has a small layout area.
摘要翻译：冗余评估电路具有（m + 1）个保险丝盒和比较器，其中m个保险丝盒输出熔丝状态地址信号，另一个保险丝盒输出比较器使能信号。每个保险丝盒有一个公共电路和k个冗余电池。 k个冗余单元共享预充电晶体管和公共电路的反相锁存器，并且所选择的冗余单元中的熔丝影响相应的保险丝盒的输出。由比较器使能信号使能的比较器比较熔丝状态地址信号和故障元件地址信号以产生冗余使能信号。冗余评估电路具有小的布局面积。

60. 发明申请

US20140301149A1 SEMICONDUCTOR MEMORY DEVICE HAVING COMPRESSION TEST MODE 有权
标题翻译：具有压缩测试模式的半导体存储器件
公开(公告)号：US20140301149A1
公开(公告)日：2014-10-09
申请号：US13859539
申请日：2013-04-09
申请人： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
发明人： Jen-Shou HSU
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C29/1201 , G11C29/14 , G11C29/40 , G11C29/48 , G11C29/50
摘要： A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing circuit, a compression circuit, and a signal distribution circuit. The memory unit comprises m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines. The timing circuit sequentially generates n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups. The compression circuit compresses data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode. The signal distribution circuit distributes signals output from the compression circuit among the i data pads in rotation. The integer n and the integer i are adjustable.
摘要翻译：提供具有压缩测试模式的半导体存储器件。半导体存储器件包括存储器单元，i测试焊盘，定时电路，压缩电路和信号分配电路。存储器单元包括分为n个激活组的m个存储器组，其中每个存储体包括用于感测和放大位线中的数据的多个感测放大器。定时电路顺序地产生n个控制信号，每个控制信号用于激活n个激活组之一中的多个感测放大器。压缩电路以压缩测试模式压缩由每个组中的多个感测放大器感测和放大的数据。信号分配电路在i数据焊盘旋转中分配从压缩电路输出的信号。整数n和整数i是可调整的。

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