专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US07746608B2 Methodology to guard ESD protection circuits against precharge effects 有权
标题翻译：保护ESD保护电路免受预充电影响的方法
公开(公告)号：US07746608B2
公开(公告)日：2010-06-29
申请号：US11548019
申请日：2006-10-10
申请人： Chih-Ming Hung , Charvaka Duvvury
发明人： Chih-Ming Hung , Charvaka Duvvury
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).
摘要翻译： ESD保护电路（710）相对于VDD焊盘（731）相对于I / O焊盘（721）和并行的第二预充电消除电路（730）由并行的第一预充电消除电路（720）保护。预充电消除电路与ESD保护电路同步，以在ESD脉冲影响I / O焊盘或VDD焊盘之前消除任何对地的预充电电压。二极管（722）连接在I / O焊盘和VDD之间。电路（720）位于I / O焊盘和接地（740）之间，由相同的VDD供电。电路（720）包括第一电阻器（723），第一nMOS晶体管（724）和包括第二电阻器（725）和第一电容器（726）的第一RC定时器。电路（730）包括第三电阻器（733），第二nMOS晶体管（734）和包括第四电阻器（735）和第二电容器（736）的第二RC定时器。

52. 发明授权

US07692504B2 Oscillator system, method of providing a resonating signal and a communications system employing the same 有权
标题翻译：振荡器系统，提供谐振信号的方法和采用该谐振信号的通信系统
公开(公告)号：US07692504B2
公开(公告)日：2010-04-06
申请号：US12030123
申请日：2008-02-12
申请人： Chih-Ming Hung , Robert B. Staszewski , Dirk Leipol
发明人： Chih-Ming Hung , Robert B. Staszewski , Dirk Leipol
IPC分类号： H03B5/18
CPC分类号： H03B5/08
摘要： An nth-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment, the nth-order oscillator system, n being greater than two, includes (1) an amplifier configured to provide an intermediate signal and (2) a feedback loop including an nth-order complex LC tank and configured to generate the resonating signal by feeding back a complex-filtered form of the intermediate signal to the amplifier.
摘要翻译：用于提供谐振信号的n阶振荡器系统，产生谐振信号的方法和通信系统。在一个实施例中，n大于2的n阶振荡器系统包括（1）被配置为提供中间信号的放大器和（2）包括第n级复数LC容器的反馈回路，并被配置为产生谐振信号通过将中间信号的复数滤波形式反馈到放大器。

53. 发明授权

US07595968B2 Circuit to reduce internal ESD stress on device having multiple power supply domains 有权
标题翻译：用于减少具有多个电源域的器件上的内部ESD应力的电路
公开(公告)号：US07595968B2
公开(公告)日：2009-09-29
申请号：US11728230
申请日：2007-03-23
申请人： Chih-Ming Hung , Charvaka Duvvury
发明人： Chih-Ming Hung , Charvaka Duvvury
IPC分类号： H02H3/22
CPC分类号： H01L27/0251 , H01L27/0266
摘要： An ESD protection circuit is designed on an integrated circuit (100) having a first power supply bus (106) and a second power supply bus (108). The circuit includes a first logic gate (116, 118) having a current path coupled to the first power supply bus. The first logic gate includes an output terminal. A second logic gate (122, 124) has a current path coupled to the second power supply bus. The second logic gate has an input terminal coupled to the output terminal of the first logic gate. A first device (306) is coupled in series with the current path of the second logic gate and is always on during normal circuit operation.
摘要翻译：在具有第一电源总线（106）和第二电源总线（108）的集成电路（100）上设计ESD保护电路。电路包括具有耦合到第一电源总线的电流通路的第一逻辑门（116,118）。第一逻辑门包括输出端。第二逻辑门（122,124）具有耦合到第二电源总线的电流路径。第二逻辑门具有耦合到第一逻辑门的输出端的输入端。第一装置（306）与第二逻辑门的电流路径串联耦合，并且在正常电路操作期间始终导通。

54. 发明授权

US07566970B2 Stacked bump structure and manufacturing method thereof 有权
标题翻译：堆叠凸块结构及其制造方法
公开(公告)号：US07566970B2
公开(公告)日：2009-07-28
申请号：US11535498
申请日：2006-09-27
申请人： Chih-Ming Hung
发明人： Chih-Ming Hung
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/85 , H01L23/52 , H01L24/03 , H01L24/11 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L24/81 , H01L2224/03 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/1134 , H01L2224/13144 , H01L2224/1613 , H01L2224/45144 , H01L2224/4809 , H01L2224/48091 , H01L2224/4813 , H01L2224/48464 , H01L2224/48482 , H01L2224/48624 , H01L2224/78301 , H01L2224/81194 , H01L2224/81801 , H01L2224/85051 , H01L2224/85399 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A method for manufacturing a stacked bump structure including the following steps is provided. First, a substrate having multiple bonding pads disposed on a surface thereof is provided. Next, a first bump and a second bump are respectively formed on any two adjacent bonding pads of the substrate. Then, a third bump is formed between the first bump and the second bump by wire bonding technology, so as to make the two adjacent bonding pads electrically connected to each other through the third bump.
摘要翻译：提供一种用于制造包括以下步骤的堆叠凸块结构的方法。首先，提供具有设置在其表面上的多个接合焊盘的基板。接下来，在衬底的任何两个相邻的焊盘上分别形成第一凸块和第二凸块。然后，通过引线接合技术在第一凸块和第二凸块之间形成第三凸块，以使两个相邻的焊盘通过第三凸块彼此电连接。

55. 发明授权

US07212387B2 Electrostatic discharge protection device including precharge reduction 有权
标题翻译：静电放电保护装置包括预充电减少
公开(公告)号：US07212387B2
公开(公告)日：2007-05-01
申请号：US10944299
申请日：2004-09-17
申请人： Charvaka Duvvury , Chih-Ming Hung
发明人： Charvaka Duvvury , Chih-Ming Hung
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： ESD protection circuitry for a signal power supply pad (801) comprising a discharge circuit (802) operable to discharge the ESD pulse to ground, and a precharge reduction circuit (810) in parallel with the discharge circuit. This precharge reduction circuit is operable to cancel any precharge voltage to ground before an ESD event, and also to discharge any trailing pulse to ground after an ESD event. The reduction circuit comprises a discharge resistor (811), preferably about 10 kΩ, connected to the discharge circuit, and a control MOS transistor (812) in series with the discharge resistor. The transistor source (812a) is connected to the resistor, the drain (812b) to ground, and the gate (812c) to core power (813) so that the transistor is shut off during IC operation and conducting when pre-charge or post-charge is present at an ESD pulse.
摘要翻译：包括用于将ESD脉冲放电到地的放电电路（802）的信号电源焊盘（801）的ESD保护电路和与放电电路并联的预充电降压电路（810）。该预充电降低电路可操作以在ESD事件之前抵消对地的任何预充电电压，并且还在ESD事件之后将任何后续脉冲放电到地。还原电路包括连接到放电电路的放电电阻（811），优选约10kΩ，以及与放电电阻串联的控制MOS晶体管（812）。晶体管源极（812a）连接到电阻器，漏极（812b）接地，栅极（812c）连接到核心功率（813），使得晶体管在IC操作期间被切断，充电或后充电存在于ESD脉冲。

56. 发明申请

US20070008199A1 Negative contributive offset compensation in a transmit buffer utilizing inverse clocking 有权
标题翻译：使用反向时钟的发送缓冲器中的负贡献偏移补偿
公开(公告)号：US20070008199A1
公开(公告)日：2007-01-11
申请号：US11178993
申请日：2005-07-11
申请人： Sameh Rezeq , Dirk Leipold , Robert Staszewski , Chih-Ming Hung
发明人： Sameh Rezeq , Dirk Leipold , Robert Staszewski , Chih-Ming Hung
IPC分类号： H03M1/06
CPC分类号： H03F1/0205 , H03F1/3241 , H03F2200/331 , H03F2200/375 , H03M3/356 , H03M3/50 , H03M7/3026 , H03M7/3037 , H04L27/368
摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
摘要翻译：一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。来自Σ-Δ调制器的正输出的处理方式与负输出不同。与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。时钟的非反相版本与正输出一起使用，反时限与负输出一起使用。使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。结果是具有零偏移的偏移补偿RF输出信号。

57. 发明授权

US07035750B2 On-chip test mechanism for transceiver power amplifier and oscillator frequency 有权
标题翻译：收发器功率放大器和振荡器频率的片上测试机制
公开(公告)号：US07035750B2
公开(公告)日：2006-04-25
申请号：US10759912
申请日：2004-01-16
申请人： Elida Isabel de Obaldia , Chih-Ming Hung , Dirk Leipold , Oren Eliezer
发明人： Elida Isabel de Obaldia , Chih-Ming Hung , Dirk Leipold , Oren Eliezer
IPC分类号： G01R31/00
CPC分类号： H03K5/08 , H04B17/102 , H04B17/16 , H04B17/20
摘要： An on-chip test mechanism for transceiver power amplifier and oscillator frequency for use with the transmitter portion of an integrated RF transceiver. The RF output from the power amplifier in the transmitter is input to a built-in dedicated analog comparator having a configurable threshold. The threshold is adjusted to a predetermined level at which crossings start to occur at the comparator output. The comparator outputs pulses only if the power amplifier output is above a minimum configurable level. The comparator output is input to a frequency divider whose frequency output is tested by a low cost external tester to determine the actual RF frequency thereby confirming generation of the correct oscillator frequency and that the amplitude of the signal at the output of the power amplifier is sufficiently high for the configurable threshold level to be exceeded, thereby determining the compliance of the output power with its defined specifications.
摘要翻译：用于收发器功率放大器和振荡器频率的片上测试机制，用于集成RF收发器的发射器部分。发射机功率放大器的RF输出被输入到具有可配置阈值的内置专用模拟比较器。阈值被调整到在比较器输出处开始发生交叉的预定电平。仅当功率放大器输出高于最小可配置电平时，比较器才会输出脉冲。比较器输出被输入到分频器，其频率输出由低成本外部测试仪测试以确定实际RF频率，从而确认产生正确的振荡器频率，并且功率放大器输出端的信号幅度足够可以超过可配置的阈值电平，从而确定输出功率与其规定的规格的一致性。

58. 发明授权

US07023272B2 Multi-band low noise amplifier system 有权
标题翻译：多频段低噪声放大器系统
公开(公告)号：US07023272B2
公开(公告)日：2006-04-04
申请号：US10827577
申请日：2004-04-19
申请人： Chih-Ming Hung , Dirk Leipold , Yo-Chuol Ho
发明人： Chih-Ming Hung , Dirk Leipold , Yo-Chuol Ho
IPC分类号： H03F3/68
CPC分类号： H03F3/45179 , H03F1/223 , H03F1/565 , H03F3/193 , H03F2200/294 , H03F2200/372 , H03F2200/492 , H03F2203/45394 , H03F2203/7209
摘要： A low noise amplifier (LNA) operates over multiple frequency bands while occupying less silicon area than known LNA implementations. The LNA includes output matching that can be tuned by an adjustable inductor together with a tunable capacitor bank.
摘要翻译：低噪声放大器（LNA）在多个频带上工作，而占用比已知LNA实现更少的硅面积。 LNA包括可调谐电感器和可调电容器组一起调谐的输出匹配。

59. 发明授权

US07006813B2 Efficient charge transfer using a switched capacitor resistor 有权
公开(公告)号：US07006813B2
公开(公告)日：2006-02-28
申请号：US10147784
申请日：2002-05-16
申请人： Robert B. Staszewski , Khurram Muhammad , Chih-Ming Hung , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Chih-Ming Hung , Dirk Leipold
IPC分类号： H04B1/26
CPC分类号： H03D7/125 , H04B1/1036
摘要： The application of a non-zero voltage offset to rotating capacitors 1111 and 1112 permit the use of a single positive voltage supply. However, the precharging of the rotating capacitors 1111 and 1112 is power inefficient. A power efficient and low-noise precharging operation is realized through the sharing of the charge on a feedback capacitor 1075 and 1080 that is significantly larger than the rotating capacitors 1111. Once a precharging operation is complete, the charge on the feedback capacitor 1075 and 1080 is refreshed from its residual charge level (rather than zero charge level) to a desired charge level.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式