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41. 发明申请

US20120153387A1 TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM 有权
标题翻译：具有高浓度的硼氢化锗的晶体管
公开(公告)号：US20120153387A1
公开(公告)日：2012-06-21
申请号：US12975278
申请日：2010-12-21
申请人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。这些技术可以例如在平面或非平面晶体管器件中实现。

42. 发明授权

US5272095A Method of manufacturing heterojunction transistors with self-aligned metal contacts 失效
标题翻译：具有自对准金属触点的异质结晶体管的制造方法
公开(公告)号：US5272095A
公开(公告)日：1993-12-21
申请号：US853439
申请日：1992-03-18
申请人： Paul M. Enquist , David B. Slater, Jr.
发明人： Paul M. Enquist , David B. Slater, Jr.
IPC分类号： H01L21/331 , H01L21/334 , H01L21/60 , H01L29/08 , H01L29/737 , H01L21/265 , H01L29/70
CPC分类号： H01L21/76897 , H01L29/0817 , H01L29/66318 , H01L29/66931 , H01L29/7371 , Y10S148/072
摘要： A method of manufacturing heterojunction transistors having self-aligned contacts. In manufacturing a heterojunction bipolar transistor, a collector and a base layer are deposited on a substrate. A masking layer is deposited on the base layer and selectively etched to form an aperture therein, exposing the base layer. An emitter having a mesa structure is grown epitaxially on the exposed base layer to produce lateral overhang portions. The overhang portions may be formed by continuing the epitaxial growth to form lateral overgrowth portions overlapping the masking material. The masking layer is removed and self-aligned contacts are formed to the base and emitter regions using the lateral overhang portions which provide separation between the emitter structure and the contacts to the base layer.
摘要翻译：一种具有自对准触点的异质结晶体管的制造方法。在制造异质结双极晶体管时，将集电极和基极层沉积在衬底上。掩模层沉积在基层上并选择性地蚀刻以在其中形成孔，暴露基层。具有台面结构的发射体在暴露的基底层上外延生长以产生横向伸出部分。可以通过继续外延生长形成与掩模材料重叠的横向过度生长部分来形成突出部分。去除掩模层，并使用提供发射极结构和与基底层的触点之间的间隔的横向突出部分，将基底和发射极区域形成自对准触点。

43. 发明公开

US20240021712A1 A NOVEL TRANSISTOR DEVICE 审中-公开
公开(公告)号：US20240021712A1
公开(公告)日：2024-01-18
申请号：US18256727
申请日：2021-12-09
申请人： Search For The Next, LTD
发明人： David SUMMERLAND , Roger LIGHT , Luke KNIGHT
IPC分类号： H01L29/735 , H01L29/66 , H01L29/73 , H01L29/08 , H01L29/10 , H01L27/082 , H01L21/3205
CPC分类号： H01L29/735 , H01L29/66931 , H01L29/6625 , H01L29/7302 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L27/082 , H01L21/32055
摘要： A bipolar transistor having a semiconductor structure that includes a channel of semiconductor type that is the same as the collector and emitter regions. The channel is significantly shallower than the base region with which it interfaces. The semiconductor structure provides improved current gain. It also enables the device to operate, when on, selectively either with primarily unipolar conduction or with primarily bipolar conduction by control of the voltage across the emitter and collector terminals of the transistor.

44. 发明授权

US10879353B2 Selective germanium P-contact metalization through trench 有权
公开(公告)号：US10879353B2
公开(公告)日：2020-12-29
申请号：US16722855
申请日：2019-12-20
申请人： Intel Corporation
发明人： Glenn A. Glass , Anand S. Murthy , Tahir Ghani
IPC分类号： H01L29/06 , H01L21/285 , H01L29/165 , H01L29/45 , H01L29/49 , H01L29/66 , H01L29/78 , H01L29/423 , H01L29/167 , H01L21/02 , H01L29/08 , H01L29/36 , H01L27/092 , H01L23/535 , H01L29/417 , H01L21/3215 , H01L21/768 , H01L29/778
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/086 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/6659 , H01L29/66477 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/785 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

45. 发明授权

US09722023B2 Selective germanium P-contact metalization through trench 有权
公开(公告)号：US09722023B2
公开(公告)日：2017-08-01
申请号：US15162551
申请日：2016-05-23
申请人： Intel Corporation
发明人： Glenn A. Glass , Anand S. Murthy , Tahir Ghani
IPC分类号： H01L31/00 , H01L29/06 , H01L21/285 , H01L29/165 , H01L29/45 , H01L29/49 , H01L29/66 , H01L29/78 , H01L29/167 , H01L21/02 , H01L29/08 , H01L29/36 , H01L27/092 , H01L23/535 , H01L29/417
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

46. 发明授权

US08901537B2 Transistors with high concentration of boron doped germanium 有权
标题翻译：具有高浓度硼掺杂锗的晶体管
公开(公告)号：US08901537B2
公开(公告)日：2014-12-02
申请号：US12975278
申请日：2010-12-21
申请人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC分类号： H01L21/285 , H01L29/165 , H01L29/167 , H01L29/49 , H01L29/78 , H01L29/66 , H01L29/45
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。这些技术可以例如在平面或非平面晶体管器件中实现。

47. 发明申请

US20130240989A1 SELECTIVE GERMANIUM P-CONTACT METALIZATION THROUGH TRENCH 有权
公开(公告)号：US20130240989A1
公开(公告)日：2013-09-19
申请号：US13990238
申请日：2011-09-30
申请人： Glenn A. Glass , Anand S. Murthy , Tahir Ghani
发明人： Glenn A. Glass , Anand S. Murthy , Tahir Ghani
IPC分类号： H01L29/167
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

48. 发明授权

US07879679B2 Electronic component manufacturing method 有权
标题翻译：电子元件制造方法
公开(公告)号：US07879679B2
公开(公告)日：2011-02-01
申请号：US12059497
申请日：2008-03-31
申请人： Oliver Kermarrec , Daniel Bensahel , Yves Campidelli
发明人： Oliver Kermarrec , Daniel Bensahel , Yves Campidelli
IPC分类号： H01L21/331
CPC分类号： H01L29/66931 , H01L29/66136 , H01L29/861 , H01L29/945
摘要： A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.
摘要翻译：一种在半导体衬底上制造电子部件的方法，包括在所述衬底中形成至少一个开口; 在所述开口的底部和所述壁的所述基板上形成交替连续的第一材料层和第二材料层，所述第二材料相对于所述第一材料和所述基板可选择性地蚀刻; 修剪不位于开口中的第一材料和第二材料的层部分; 选择性蚀刻第一材料的一部分以获得沟槽; 并用至少一个第三材料填充沟槽。

49. 发明申请

US20070284640A1 SEMICONDUCTOR CAPACITORS IN HOT (HYBRID ORIENTATION TECHNOLOGY) SUBSTRATES 失效
标题翻译：半导体电容器（混合方向技术）衬底
公开(公告)号：US20070284640A1
公开(公告)日：2007-12-13
申请号：US11423284
申请日：2006-06-09
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L29/66931
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.
摘要翻译：半导体结构及其形成方法。半导体结构包括半导体衬底。半导体结构还包括在半导体衬底的顶部上的电绝缘区域。半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。半导体结构还包括在绝缘区域的顶部上的第二半导体区域。半导体结构还包括在第一半导体区域和半导体衬底中的电容器。半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。

50. 发明授权

US5444267A Quantum device utilizing the quantum effect 失效
标题翻译：使用量子效应的量子器件
公开(公告)号：US5444267A
公开(公告)日：1995-08-22
申请号：US331270
申请日：1994-10-28
申请人： Kenji Okada , Kiyoshi Morimoto , Masaharu Udagawa , Koichiro Yuki , Masaaki Niwa , Yoshihiko Hirai , Juro Yasui
发明人： Kenji Okada , Kiyoshi Morimoto , Masaharu Udagawa , Koichiro Yuki , Masaaki Niwa , Yoshihiko Hirai , Juro Yasui
IPC分类号： H01L29/06 , H01L21/334 , H01L29/10 , H01L29/68 , H01L29/772 , H01L29/88 , H01L29/161
CPC分类号： B82Y10/00 , B82Y30/00 , H01L29/1037 , H01L29/66931 , H01L29/772 , H01L29/882 , Y10S438/911 , Y10S438/962
摘要： A quantum device including a plate-like conductor part having a necking portion made by forming a first mask layer having a first strip portion on a conductor substrate; forming a second mask layer having a second strip portion on the conductor substrate; etching a region of the conductor substrate which is not covered with the first and second mask layers, by using the first and second mask layers as an etching mask, to form a plurality of first recess portions on a surface of the conductor substrate; selectively covering side faces of the plurality of first recess portions, and side faces of the first and second mask layers with a side wall film; selectively removing only the second mask layer; etching another region of the conductor substrate which is not covered with the first mask layer and the side wall film, by using the first mask layer and the side wall film as an etching mask, to form a plurality of second recess portions on the surface of the conductor substrate; selectively removing part of another region of the surface of the conductor substrate which is not covered with the first mask layer and the side wall film; and removing the first mask layer and the side wall film, to form the plate-like conductor part having the necking portion.
摘要翻译：公开了一种包括具有颈缩部的板状导体部的量子装置及其制造方法。该方法包括以下步骤：在导体基板上形成具有第一条带部分的第一掩模层; 在所述导体基板上形成具有第二条带部分的第二层; 通过使用第一和第二掩模层作为蚀刻掩模蚀刻未被第一和第二掩模层覆盖的导体基板的区域，以在导体基板的表面上形成多个第一凹部; 选择性地覆盖所述多个第一凹部的侧面，所述第一和第二掩模层的侧面具有侧壁膜; 选择性地除去第二掩模层，第一掩模层和侧壁膜被去除; 通过使用第一掩模层和侧壁膜作为蚀刻来蚀刻未被第一掩模层和侧壁膜覆盖的导体基板的另一区域，以在第一掩模层和侧壁膜的表面上形成多个第二凹部基体; 选择性地去除未被第一掩模层和侧壁膜覆盖的导体基板的表面的另一区域的一部分; 并且去除第一掩模层和侧壁膜，以在导体基板上形成具有颈缩部分的板状导体部分。

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