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41. 发明申请

US20100193957A1 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100193957A1
公开(公告)日：2010-08-05
申请号：US12759335
申请日：2010-04-13
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L23/532
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {l ap−anl/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {lbp−bn l/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp) }
摘要翻译：提供的是具有分层互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜被接触与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使得构成具有导体膜的最小自由能和短边的平面的矩形单位电池的短边面ap之间的差，，构成具有相邻膜的最小自由能的平面的矩形单位电池，即{l ap-anl / ap}×100 = A（％）和矩形单元电池的长边，bp之间的差异，构成具有相邻膜的最小自由能的构成平面的矩形单元电池的导体膜和长边bn的最小自由能的平面{lbp-bn l / bp}×100 = B（％）满足{A + B×（ap / bp）} <13的不等式。在此，导体膜的扩散被延迟。

42. 发明授权

US07253103B2 Method for producing semiconductor devices that includes forming a copper film in contact with a ruthenium film 有权
标题翻译：包括形成与钌膜接触的铜膜的半导体器件的制造方法
公开(公告)号：US07253103B2
公开(公告)日：2007-08-07
申请号：US11392540
申请日：2006-03-30
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L21/443
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：提供了一种具有层状互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使构成具有最小自由能的平面的矩形单元电池的短边，即< 导体薄膜和构成具有相邻薄膜的最小自由能的平面的矩形单元电池的短边，即_{n x100 = A（％）和构成该矩阵单位单元的长边，b P 之间的差异构成具有相邻膜的最小自由能的平面的矩形单位电池的导体膜和长边的最小自由能的平面{| b＆lt; p＆lt; x100 = B（％）满足{A + Bx（a _{p b＆lt; p＆lt; p＆gt;）} <13。在此，导体膜的扩散被延迟。}}

43. 发明授权

US07135732B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07135732B2
公开(公告)日：2006-11-14
申请号：US10479703
申请日：2002-06-04
申请人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
发明人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
IPC分类号： H01L27/108
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L21/31604 , H01L27/10814 , H01L28/40 , H01L28/60 , H01L29/513
摘要： In order to supply a semiconductor device having high-reliability, there are used a first capacitor electrode, a capacitor insulating film formed in contact with the first capacitor electrode and mainly composed of titanium oxide, and a second capacitor electrode formed in contact with the capacitor insulating film, and there is used a conductive oxide film mainly composed of ruthenium oxide or iridium oxide for the first capacitor electrode and the second capacitor electrode. Alternatively, there is used a gate insulating film having a titanium silicate film and titanium oxide which suppress leakage current.
摘要翻译：为了提供具有高可靠性的半导体器件，使用第一电容器电极，形成为与第一电容器电极接触并主要由氧化钛构成的电容器绝缘膜，以及形成为与电容器接触的第二电容器电极并且使用主要由氧化钌或氧化铱构成的导电氧化物膜用于第一电容器电极和第二电容器电极。或者，使用具有抑制漏电流的钛硅酸盐膜和氧化钛的栅极绝缘膜。

44. 发明授权

US06940118B2 Semiconductor device with high permittivity gate dielectric film 有权
标题翻译：具有高介电常数栅极介电膜的半导体器件
公开(公告)号：US06940118B2
公开(公告)日：2005-09-06
申请号：US10299197
申请日：2002-11-18
申请人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
发明人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
IPC分类号： H01L21/02 , H01L21/28 , H01L21/316 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/105 , H01L27/108 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L21/31641 , H01L21/31645 , H01L27/10873 , H01L28/56 , H01L28/57 , H01L29/4975 , H01L29/513
摘要： A semiconductor device has a gate dielectric film formed of zirconium oxide or hafnium oxide as a chief material and a gate electrode film in contact with the gate dielectric film on one principal surface side of a silicon substrate. The gate dielectric film contains an addition element to prevent diffusion of oxygen.
摘要翻译：半导体器件具有由氧化锆或氧化铪形成的栅极电介质膜和与硅衬底的一个主表面侧的栅极电介质膜接触的栅电极膜。栅极电介质膜含有防止氧扩散的添加元素。

45. 发明授权

US06927435B2 Semiconductor device and its production process 失效
标题翻译：半导体器件及其生产工艺
公开(公告)号：US06927435B2
公开(公告)日：2005-08-09
申请号：US10043099
申请日：2002-01-14
申请人： Hiroshi Moriya , Tomio Iwasaki , Hideo Miura , Shuji Ikeda
发明人： Hiroshi Moriya , Tomio Iwasaki , Hideo Miura , Shuji Ikeda
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/76 , H01L21/336 , H01L27/108
CPC分类号： H01L21/823462 , H01L21/823456
摘要： A semiconductor device comprising a semiconductor substrate, gate insulators formed on the substrate, and gate electrodes formed on the gate insulators, the gate insulators which are mainly composed of a material selected from titanium oxide, zirconium oxide and hafnium oxide, and in which compressive strain is produced and equipped with MOS transistors, can suppress leakage current flowing through the gate insulators and has high reliability.
摘要翻译：一种半导体器件，包括半导体衬底，形成在衬底上的栅极绝缘体和形成在栅极绝缘体上的栅极电极，主要由选自氧化钛，氧化锆和氧化铪的材料组成的栅极绝缘体，并且其中压缩应变制造并配备有MOS晶体管，可以抑制流过栅极绝缘体的漏电流并具有高可靠性。

46. 发明授权

US06545362B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US06545362B2
公开(公告)日：2003-04-08
申请号：US09941616
申请日：2001-08-30
申请人： Hiroshi Moriya , Tomio Iwasaki , Hideo Miura , Shinji Nishihara , Masashi Sahara
发明人： Hiroshi Moriya , Tomio Iwasaki , Hideo Miura , Shinji Nishihara , Masashi Sahara
IPC分类号： H01L2352
CPC分类号： H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.

47. 发明授权

US06271559B1 Semiconductor memory with information storage capacitance including an electrode containing precious metal and an added element 失效
标题翻译：具有信息存储电容的半导体存储器包括含有贵金属的电极和添加元素
公开(公告)号：US06271559B1
公开(公告)日：2001-08-07
申请号：US09185632
申请日：1998-11-04
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/10852 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： A semiconductor memory includes a structure in which an insulating film is formed on a transistor constituted by a gate oxide film, a gate electrode and diffusion regions, an information storage capacitance device is formed on the insulating film and is connected to the diffusion layer through a polycrystalline silicon film. The capacitance device includes a bottom electrode formed by laminating an electrically conductive film and a precious metal film, an oxide film and a top electrode. The precious metal film contains an additional element having a smaller atomic radius than that of a precious metal element as a main constituent element besides the precious metal element, and interatomic bond energy between this additional element and the precious metal element is within ±20 % of interatomic bond energy between the precious metal elements. This structure can restrict the grain boundary diffusion of oxygen in the precious metal film as well as oxidation of the electrically conductive film, can prevent delamination between the conductive film and the precious metal film, and can prevent conduction failures.
摘要翻译：半导体存储器包括在由栅极氧化膜，栅电极和扩散区构成的晶体管上形成绝缘膜的结构，在绝缘膜上形成信息容纳电容元件，并且通过一个多晶硅膜。电容器件包括通过层压导电膜和贵金属膜，氧化物膜和顶部电极而形成的底部电极。贵金属膜除了贵金属元素之外还含有比作为主要构成元素的贵金属元素小的原子半径的附加元素，并且该附加元素和贵金属元素之间的原子间键能在±20％以内贵金属元素之间的原子间键能量。该结构可以限制贵金属膜中的氧的晶界扩散以及导电膜的氧化，可以防止导电膜和贵金属膜之间的分层，并且可以防止导电故障。

48. 发明授权

US07459786B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07459786B2
公开(公告)日：2008-12-02
申请号：US11155272
申请日：2005-06-17
申请人： Hiromi Shimazu , Tomio Iwasaki , Hiroyuki Ohta , Kensuke Ishikawa , Osamu Inoue , Takayuki Oshima
发明人： Hiromi Shimazu , Tomio Iwasaki , Hiroyuki Ohta , Kensuke Ishikawa , Osamu Inoue , Takayuki Oshima
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/5222 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the multilayer wiring structure, a first insulation layer having a high barrier property and a compression stress, and making contact with the upper surface of a first wiring made of copper as a main component material, a second insulation film having a tensile stress, and a third insulation film having a dielectric constant which is lower than those of the first and second insulation film, are laminated one upon another in the mentioned order as viewed the bottom thereof, and a via hole is formed piercing through the first insulation film, the second insulation film and the third insulation film, making contact with the first wiring.
摘要翻译：具有由铜作为主要成分材料形成的多层布线结构的可靠的半导体器件，其限制由应力迁移引起的空隙的发生。在多层布线结构体中，具有高阻隔性和压缩应力的第一绝缘层，与由铜作为主要成分材料的第一布线的上表面接触，具有拉伸应力的第二绝缘膜，以及具有低于第一绝缘膜和第二绝缘膜的介电常数的第三绝缘膜按照从底部开始的顺序依次层叠，并且形成穿过第一绝缘膜的通孔，第二绝缘膜和第三绝缘膜，与第一布线接触。

49. 发明申请

US20060006543A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060006543A1
公开(公告)日：2006-01-12
申请号：US11155272
申请日：2005-06-17
申请人： Hiromi Shimazu , Tomio Iwasaki , Hiroyuki Ohta , Kensuke Ishikawa , Osamu Inoue , Takayuki Oshima
发明人： Hiromi Shimazu , Tomio Iwasaki , Hiroyuki Ohta , Kensuke Ishikawa , Osamu Inoue , Takayuki Oshima
IPC分类号： H01L23/48
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/5222 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the multilayer wiring structure, a first insulation layer having a high barrier property and a compression stress, and making contact with the upper surface of a first wiring made of copper as a main component material, a second insulation film having a tensile stress, and a third insulation film having a dielectric constant which is lower than those of the first and second insulation film, are laminated one upon another in the mentioned order as viewed the bottom thereof, and a via hole is formed piercing thorough the first insulation film, the second insulation film and the third insulation film, making contact with the first wiring.
摘要翻译：具有由铜作为主要成分材料形成的多层布线结构的可靠的半导体器件，其限制由应力迁移引起的空隙的发生。在多层布线结构体中，具有高阻隔性和压缩应力的第一绝缘层，与由铜作为主要成分材料的第一布线的上表面接触，具有拉伸应力的第二绝缘膜，以及介电常数低于第一绝缘膜和第二绝缘膜的介电常数的第三绝缘膜按照其底部的顺序一个接一个层叠，并且形成穿过第一绝缘膜的通孔，第二绝缘膜和第三绝缘膜，与第一布线接触。

50. 发明授权

US07279769B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07279769B2
公开(公告)日：2007-10-09
申请号：US11139002
申请日：2005-05-25
申请人： Norio Ishitsuka , Jun Tanaka , Tomio Iwasaki , Hiroyuki Ohta
发明人： Norio Ishitsuka , Jun Tanaka , Tomio Iwasaki , Hiroyuki Ohta
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/823481 , H01L21/02134 , H01L21/02137 , H01L21/02203 , H01L21/3124 , H01L21/31662 , H01L29/7833
摘要： To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an element isolation trench located between the element formation regions and having an element isolation insulating film embedded therein, and a gate insulating film, a gate electrode and a plurality of interconnect layers formed thereabove, each formed in the element formation region, wherein the element isolation trench has a thermal oxide film formed between the semiconductor substrate and the element isolation insulating film, and the element isolation film has a great number of micro-pores formed inside thereof and is more porous than the thermal oxide film.
摘要翻译：为了抑制在栅电极的端部处的半导体器件的衬底中的位错的发生。提供了一种半导体器件，其具有形成在半导体衬底的主表面上的多个元件形成区域，位于元件形成区域之间并且具有嵌入元件隔离绝缘膜的元件隔离沟槽，以及栅极绝缘膜，栅极电极和形成在其上的多个互连层，各自形成在元件形成区域中，其中元件隔离沟槽具有形成在半导体衬底和元件隔离绝缘膜之间的热氧化膜，并且元件隔离膜具有大量在其内形成的微孔比热氧化膜多孔。

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