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1. 发明授权

US07701062B2 Semiconductor device and method for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07701062B2
公开(公告)日：2010-04-20
申请号：US11834081
申请日：2007-08-06
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：提供的是具有分层互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜被接触与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使得构成具有导体膜的最小自由能和短边的平面的矩形单位电池的短边面ap之间的差，，构成具有相邻膜的最小自由能的平面的矩形单元电池，矩形单位电池的长边，bp之间的差异为{| ap-an | / ap}×100 = A（％）构成具有相邻膜的最小自由能的构成平面的矩形单位电池的导体膜和长边bn的最小自由能的平面{| bp-bn | / bp}×100 = B （％）满足{A + B×（ap / bp）} <13的不等式。在此，导体膜的扩散被延迟。

2. 发明申请

US20060183324A1 Semiconductor device and method for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060183324A1
公开(公告)日：2006-08-17
申请号：US11392540
申请日：2006-03-30
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L21/44
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：提供了一种具有层状互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使构成具有最小自由能的平面的矩形单元电池的短边，即< 导体薄膜和构成具有相邻薄膜的最小自由能的平面的矩形单元电池的短边，即_{n x100 = A（％）和构成该矩阵单位单元的长边，b P 之间的差异构成具有相邻膜的最小自由能的平面的矩形单位电池的导体膜和长边的最小自由能的平面{| b＆lt; p＆lt; x100 = B（％）满足{A + Bx（a _{p b＆lt; p＆lt; p＆gt;）} <13。在此，导体膜的扩散被延迟。}}

3. 发明授权

US07030493B2 Semiconductor device having layered interconnect structure with a copper or platinum conducting film and a neighboring film 失效
标题翻译：具有与铜或铂导电膜和相邻膜的分层互连结构的半导体器件
公开(公告)号：US07030493B2
公开(公告)日：2006-04-18
申请号：US10878018
申请日：2004-06-29
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L23/52
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：提供了一种具有层状互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使构成具有最小自由能的平面的矩形单元电池的短边，即< 导体薄膜和构成具有相邻薄膜的最小自由能的平面的矩形单元电池的短边，即_{n x100 = A（％）和构成该矩阵单位单元的长边，b P 之间的差异构成具有相邻膜的最小自由能的平面的矩形单位电池的导体膜和长边的最小自由能的平面{| b＆lt; p＆lt; x100 = B（％）满足{A + Bx（a _{p b＆lt; p＆lt; p＆gt;）} <13。在此，导体膜的扩散被延迟。}}

4. 发明授权

US06989599B1 Semiconductor device with layered interconnect structure 失效
标题翻译：具有分层互连结构的半导体器件
公开(公告)号：US06989599B1
公开(公告)日：2006-01-24
申请号：US09255856
申请日：1999-02-23
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L23/532
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A reliable semiconductor device is provided with a layered interconnect structure that may develop no problem of voids and interconnect breakdowns, in which the layered interconnect structure includes a conductor film and a neighboring film so layered on a semiconductor substrate that the neighboring film is in contact with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：可靠的半导体器件具有分层互连结构，其不会产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻薄膜层叠在半导体衬底上，邻近薄膜与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使构成具有最小自由能的平面的矩形单元电池的短边，即< 导体薄膜和构成具有相邻薄膜的最小自由能的平面的矩形单元电池的短边，即_{n x100 = A（％）和构成该矩阵单位单元的长边，b P 之间的差异构成具有相邻膜的最小自由能的平面的矩形单位电池的导体膜和长边的最小自由能的平面{| b＆lt; p＆lt; x100 = B（％）满足{A + Bx（a _{p b＆lt; p＆lt; p＆gt;）} <13。以这种方式，导体膜的扩散被延迟。}}

5. 发明授权

US06476492B2 Semiconductor device having a capacitor and an interconnect layer with molybdenum-containing tungsten 失效
标题翻译：具有电容器的半导体器件和具有含钼钨的互连层
公开(公告)号：US06476492B2
公开(公告)日：2002-11-05
申请号：US09758288
申请日：2001-01-12
申请人： Tomio Iwasaki , Hideo Miura , Takashi Nakajima , Hiroyuki Ohta , Shinji Nishihara , Masashi Sahara
发明人： Tomio Iwasaki , Hideo Miura , Takashi Nakajima , Hiroyuki Ohta , Shinji Nishihara , Masashi Sahara
IPC分类号： H01L2348
CPC分类号： H01L23/53257 , H01L27/10814 , H01L27/10894 , H01L28/55 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, which comprises a capacitor component comprising a first electrode, an oxide film with a high dielectric constant or ferroelectricity in contact with the first electrode and a second electrode in contact with the oxide film, as formed in this order, on one principal side of a silicon substrate with a metal wiring layer formed thereon, such problems as breaking of tungsten interconnect, lowering of reliability, lowering of yield, etc. of semi-conductor devices can be solved by using molybdenum-containing tungsten as the material of metal interconnect layer.
摘要翻译：在包括第一电极的电容器组件，具有高介电常数或与第一电极接触的铁电性的氧化膜和与该氧化物膜接触的第二电极的电容器组件中，在其上形成有金属布线层的硅衬底的主面上，通过使用含钼钨作为材料，可以解决半导体器件的钨互连断裂，可靠性降低，成品率降低等问题金属互连层。

6. 发明授权

US08026609B2 Semiconductor device and method for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08026609B2
公开(公告)日：2011-09-27
申请号：US12759335
申请日：2010-04-13
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {lap−anl/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {lbp−bnl/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：提供的是具有分层互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜被接触与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使得构成具有导体膜的最小自由能和短边的平面的矩形单位电池的短边面ap之间的差，，构成相邻膜的最小自由能的平面的矩形单位电池，构成的矩形单位电池的长边，bp之间的差值，即（lap-anl / ap}×100 = A（％）构成相邻膜的最小自由能的{B1p-bnl / bp}×100 = B（％）的平面的矩形单位电池的导体膜的最小自由能和长边bn的平面满足 {A + B×（ap / bp）} <13的不等式。在此，导体膜的扩散被延迟。

7. 发明授权

US07608899B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07608899B2
公开(公告)日：2009-10-27
申请号：US11936443
申请日：2007-11-07
申请人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
发明人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L21/823462 , H01L21/28097 , H01L21/28185 , H01L21/28194 , H01L21/28518 , H01L21/31604 , H01L21/823412 , H01L27/1085 , H01L27/10873 , H01L29/045 , H01L29/4908 , H01L29/4975 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/78696
摘要： Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate lectrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.
摘要翻译：在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅极电介质膜6,7和栅极放电层8,9作为MOS晶体管。氧化锆或氧化铪被用作栅极电介质膜6,7的主要成分。例如通过CVD形成栅极绝缘膜6,7。作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。在使用其表面为（111）的基板的情况下，在使用表面为（001）晶面的硅衬底的情况下，氧的扩散系数小于氧的扩散系数的1/100，并且控制氧扩散。因此，控制氧扩散，防止漏电流的产生，提高性能。实现了具有高可靠性并且能够防止伴随小型化的特性劣化的半导体器件。

8. 发明授权

US07358578B2 Field effect transistor on a substrate with (111) orientation having zirconium oxide gate insulation and cobalt or nickel silicide wiring 有权
标题翻译：具有（111）取向的衬底上的场效应晶体管具有氧化锆栅极绝缘体和钴或镍硅化物布线
公开(公告)号：US07358578B2
公开(公告)日：2008-04-15
申请号：US10155833
申请日：2002-05-22
申请人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
发明人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/823462 , H01L21/28097 , H01L21/28185 , H01L21/28194 , H01L21/28518 , H01L21/31604 , H01L21/823412 , H01L27/1085 , H01L27/10873 , H01L29/045 , H01L29/4908 , H01L29/4975 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/78696
摘要： Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.
摘要翻译：在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅电介质膜6,7和栅电极8，以便成为MOS晶体管。氧化锆或氧化铪被用作栅介质膜6,7的主要成分。栅介质膜6,7例如通过CVD形成。作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。在使用表面为（111）晶面的基板的情况下，在使用表面为（001）晶面的硅基板的情况下，氧的扩散系数小于1/100，氧气扩散被控制。因此，控制氧扩散，防止漏电流的产生，提高性能。实现了具有高可靠性并且能够防止伴随小型化的特性劣化的半导体器件。

9. 发明申请

US20080036090A1 Semiconductor device and method for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080036090A1
公开(公告)日：2008-02-14
申请号：US11834081
申请日：2007-08-06
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L23/532
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：提供的是具有分层互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜被接触与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使构成具有最小自由能的平面的矩形单元电池的短边，即< 导体薄膜和构成具有相邻薄膜的最小自由能的平面的矩形单元电池的短边，即_{n 构成该矩阵单元的长边，b p 之间的差，x100 = A（％）构成具有相邻膜的最小自由能的平面的矩形单位电池的导体膜和长边的最小自由能的平面{| b＆lt; p＆lt; x100 = B（％）满足不等式{A + Bx（a p b＆lt; p＆lt; p＆gt;）} <13。在此，导体膜的扩散被延迟。}

10. 发明申请

US20070187823A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070187823A1
公开(公告)日：2007-08-16
申请号：US11783983
申请日：2007-04-13
申请人： Naotaka Tanaka , Tomio Iwasaki , Hideo Miura , Yasuyuki Nakajima , Tomoo Matsuzawa
发明人： Naotaka Tanaka , Tomio Iwasaki , Hideo Miura , Yasuyuki Nakajima , Tomoo Matsuzawa
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/563 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/1134 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/4807 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48453 , H01L2224/48465 , H01L2224/4851 , H01L2224/48624 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/78301 , H01L2224/85045 , H01L2224/85205 , H01L2225/06558 , H01L2225/06568 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01105 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19043 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20303 , H01L2924/20304 , H01L2924/20305 , H01L2924/20751 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2924/00015
摘要： An object of the present invention is to establish, for an LSI having a stacked interconnection structure of Cu interconnect/Low-k material, a narrow pitch wire bonding technique enabling a reduction in damage to a bonding pad and application similar to the conventional LSI of an aluminum interconnection. In a semiconductor device having a multilayer interconnection made of a Cu interconnect/Low-k dielectric material, the above-described object can be attained by a bonding pad structure in which all the wiring layers up to the uppermost cap interconnect are formed of a Cu wiring layer and a bonding pad portion formed of a Cu layer is equipped with a refractory intermediate metal layer such as Ti (titanium) filmor (tungsten) film on the Cu layer and an aluminum alloy layer on the intermediate metal layer.
摘要翻译：本发明的目的在于，对于具有Cu互连/ Low-k材料的堆叠互连结构的LSI，可以实现能够减少对焊盘的损伤的窄间距引线接合技术和类似于传统LSI的铝互连。在具有由Cu互连/ Low-k电介质材料制成的多层互连的半导体器件中，上述目的可以通过一种焊盘结构来实现，其中所有的布线层直到最上盖互连件都是由Cu 布线层和由Cu层形成的接合焊盘部分在Cu层上装有诸如Ti（钛）膜（钨）的耐火材料中间金属层和中间金属层上的铝合金层。

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