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41. 发明授权

US07279754B2 Semiconductor memory device and a method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07279754B2
公开(公告)日：2007-10-09
申请号：US10465550
申请日：2003-06-20
申请人： Masahiro Moniwa , Hiraku Chakihara , Kousuke Okuyama , Yasuhiko Takahashi
发明人： Masahiro Moniwa , Hiraku Chakihara , Kousuke Okuyama , Yasuhiko Takahashi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104
摘要： A memory cell of a SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly consist of a square pole laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
摘要翻译： SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。垂直MISFET分别主要由以下顺序层叠的下半导体层，中间半导体层和上半导体层形成的方形极板层叠，形成在层叠体的侧壁表面上的氧化硅栅极绝缘膜，以及形成为覆盖层叠体的侧壁的栅电极。垂直MISFET是完全耗尽型MISFET。

42. 发明申请

US20060202274A1 Semiconductor integrated circuit and nonvolatile memory element 失效
公开(公告)号：US20060202274A1
公开(公告)日：2006-09-14
申请号：US11430039
申请日：2006-05-09
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

43. 发明授权

US07067888B2 Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07067888B2
公开(公告)日：2006-06-27
申请号：US09985303
申请日：2001-11-02
申请人： Hideki Aono , Kousuke Okuyama , Kozo Watanabe , Kenichi Kuroda
发明人： Hideki Aono , Kousuke Okuyama , Kozo Watanabe , Kenichi Kuroda
IPC分类号： H01L29/772
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L27/105
摘要： Semiconductor regions for the suppression of short channel effects are not provided for a pMIS and an nMIS that constitute an inverter circuit of an input first stage of an I/O buffer circuit, whereas semiconductor regions for the suppression of short channel effects are provided for pMIS and nMIS of inverter circuits of the next stage of an I/O buffer circuit.
摘要翻译：对于构成I / O缓冲电路的输入第一级的反相器电路的pMIS和nMIS，不提供用于抑制短信道效应的半导体区域，而为pMIS提供用于抑制短信道效应的半导体区域和I / O缓冲电路的下一级的反相器电路的nMIS。

44. 发明授权

US07042764B2 Semiconductor integrated circuit and nonvolatile memory element 有权
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US07042764B2
公开(公告)日：2006-05-09
申请号：US11151231
申请日：2005-06-14
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： G11C16/04 , G11C14/00
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.
摘要翻译：半导体集成电路器件设置在半导体衬底上，并且包括多个字线，多条数据线，以及多个电可编程和可擦除的非易失性存储器单元，分别耦合到多条字线和多条数据线。可擦除非易失性存储单元每个都包括具有浮置栅极的MIS晶体管，该浮置栅极具有耦合到对应的数据线的第一级多晶硅层，源极和漏极，以及由半导体衬底中的半导体区域形成的控制栅极控制门被耦合到对应的字线。

45. 发明申请

US20050232008A1 Semiconductor integrated circuit and nonvolatile memory element 有权
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US20050232008A1
公开(公告)日：2005-10-20
申请号：US11151231
申请日：2005-06-14
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , G11C16/28 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.
摘要翻译：半导体集成电路器件设置在半导体衬底上，并且包括多个字线，多条数据线，以及多个电可编程和可擦除的非易失性存储器单元，分别耦合到多条字线和多条数据线。可擦除非易失性存储单元每个都包括具有浮置栅极的MIS晶体管，该浮置栅极具有耦合到对应的数据线的第一级多晶硅层，源极和漏极，以及由半导体衬底中的半导体区域形成的控制栅极控制门被耦合到对应的字线。

46. 发明授权

US06771538B2 Semiconductor integrated circuit and nonvolatile memory element 失效
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US06771538B2
公开(公告)日：2004-08-03
申请号：US10610567
申请日：2003-07-02
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： G11C1604
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.
摘要翻译：由于上述原因，即使采用诸如单层多晶硅栅极工艺的单层栅极工艺，也可以获得其中合并数据保存能力优异的非易失性存储器的系统LSI等半导体集成电路，与DRAM等一起封装。此外，由于可以形成高可靠性的非易失性存储器，而不需要对诸如标准CMOS制造工艺的现有技术制造工艺增加任何步骤，本发明可以容易地应用于其中非易失性存储器和逻辑LSI，或者非易失性存储器和DRAM被合并并封装在相同的半导体衬底上。因此，可以在不增加制造成本的情况下提供闪存被合并和打包的系统LSI。

47. 发明授权

US06614684B1 Semiconductor integrated circuit and nonvolatile memory element 有权
标题翻译：半导体集成电路和非易失性存储元件
公开(公告)号：US06614684B1
公开(公告)日：2003-09-02
申请号：US09493280
申请日：2000-01-28
申请人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
发明人： Shoji Shukuri , Kazuhiro Komori , Katsuhiko Kubota , Kousuke Okuyama
IPC分类号： G11C1604
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： An information retention capability based on a memory cell which includes pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.
摘要翻译：提高了基于包含差分形式的一对非易失性存储器元件的存储单元的信息保持能力。构成闪速存储器的非易失性存储元件（130）被构造成通过利用晶体管的栅极氧化膜（GT2）和栅电极（GT2）分别形成隧道氧化膜（GO3）和浮栅电极（FGT）用于形成在与元件（130）的半导体衬底相同的半导体衬底上的电路。存储单元以2单元/ 1位方案构成，其中一对非易失性存储器元件可以分别连接到一对互补数据线，并且为非易失性存储元件设置彼此不同的阈值电压状态以便差异地读出数据。读出模式中的字线电压被设定为与热平衡状态（初始阈值电压）中的阈值电压基本相等，并且基本上等于低阈值电压值和高阈值的平均值电压值。因此，增强数据保持能力以实现读出故障率的降低。

48. 发明授权

US5610089A Method of fabrication of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件制造方法
公开(公告)号：US5610089A
公开(公告)日：1997-03-11
申请号：US429868
申请日：1995-04-27
申请人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
发明人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
IPC分类号： H01L21/8238 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L29/78
CPC分类号： H01L27/10873 , H01L21/823864 , H01L27/0251 , H01L27/0266 , H01L27/0922 , H01L29/78 , H01L29/7836
摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
摘要翻译：公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

49. 发明授权

US5534723A Semiconductor integrated circuit device having output and internal circuit MISFETS 失效
标题翻译：具有输出和内部电路MISFETS的半导体集成电路器件
公开(公告)号：US5534723A
公开(公告)日：1996-07-09
申请号：US431568
申请日：1995-04-27
申请人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
发明人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
IPC分类号： H01L21/8238 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L29/78 , H01L29/06
CPC分类号： H01L21/823864 , H01L27/0251 , H01L27/0266 , H01L27/0922 , H01L27/10873 , H01L29/78
摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
摘要翻译：公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

50. 发明授权

US4818716A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US4818716A
公开(公告)日：1989-04-04
申请号：US111690
申请日：1987-10-22
申请人： Kousuke Okuyama , Ken Uchida , Kouichi Kusuyama , Satoshi Meguro , Hisao Katto , Kazuhiro Komori
发明人： Kousuke Okuyama , Ken Uchida , Kouichi Kusuyama , Satoshi Meguro , Hisao Katto , Kazuhiro Komori
IPC分类号： H01L27/112 , H01L21/8246 , H01L21/265 , B01J17/00
CPC分类号： H01L27/1126
摘要： Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.
摘要翻译：公开了具有串联连接的多个MISFET的垂直型只读存储器（ROM）的存储单元。 MISFET包括形成有多个导电层的栅电极，其中一些MISFET被设置为耗尽型，并且至少一些剩余的MISFET被设置为增强型，以便将信息写入存储单元。信息写入操作通过至少两个步骤进行。也就是说，在第一信息写入步骤中，使用栅电极作为掩模来注入杂质; 并且在第二步骤中，通过栅电极将杂质注入到半导体衬底的表面中。这些步骤使得能够生产半导体存储器件，例如具有降低的串联电阻并且适于高度集成的存储单元的垂直型掩模ROM。此外，公开了一种半导体存储器件的存储结构，其适用于通过多层栅电极的布置而具有更高的集成度。

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