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41. 发明申请

US20130058173A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130058173A1
公开(公告)日：2013-03-07
申请号：US13607306
申请日：2012-09-07
申请人： Shuuichi SENOU , Kenjyu Shimogawa , Susumu Takano , Toshihiko Funaki , Hideaki Arima
发明人： Shuuichi SENOU , Kenjyu Shimogawa , Susumu Takano , Toshihiko Funaki , Hideaki Arima
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G06F3/0635 , G06F13/4022
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.
摘要翻译：根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，存储第一和第二模式信息的模式信息存储单元，能够通过第一总线接口设置的第一和第二模式信息电路，基于第一模式信息操作的第一存储器核心，第一存储器核心连接到第一总线接口电路并被提供有第一时钟信号，第二存储器内核，第二存储器核心被提供有第二存储器核心时钟信号和选择电路，其基于预定的切换信息选择性地将第二存储器核心连接到第一或第二总线接口电路，其中当第二存储器核心连接到第二存储器核心时，第二存储器核心基于第二模式信息操作第二总线接口电路。

42. 发明授权

US08362799B2 Semiconductor device, and failure detection system and failure detection method of data hold circuit 有权
标题翻译：半导体器件，数据保持电路的故障检测系统和故障检测方法
公开(公告)号：US08362799B2
公开(公告)日：2013-01-29
申请号：US13064480
申请日：2011-03-28
申请人： Hideaki Arima
发明人： Hideaki Arima
IPC分类号： H03K19/003
CPC分类号： H03K19/23 , H03K19/00392
摘要： A semiconductor device according to a first aspect of the present invention includes: a first circuit that outputs a first output value having a majority of output values received from N (N is three or more odd numbers) pieces of data hold circuits receiving a same input value; and a second circuit that outputs a second output value which is less than the majority of output values received from the N pieces of the data hold circuits.
摘要翻译：根据本发明的第一方面的半导体器件包括：第一电路，其输出从N（N是三个或更多个奇数）个数据保持电路接收的具有大量输出值的第一输出值，所述数据保持电路接收相同的输入值; 以及第二电路，其输出小于从N个数据保持电路接收的输出值的大部分的第二输出值。

43. 发明授权

US5949110A DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof 失效
标题翻译：具有通过利用衬垫层使MOS晶体管的源极 - 漏极互连接触小的外围电路的DRAM及其制造方法
公开(公告)号：US5949110A
公开(公告)日：1999-09-07
申请号：US877800
申请日：1997-06-18
申请人： Hideaki Arima
发明人： Hideaki Arima
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10852 , H01L27/105 , H01L27/10817 , Y10S257/903
摘要： A MOS transistor included in a peripheral circuit of a DRAM has conductive layers for interconnection on respective surfaces of a pair of source.multidot.drain regions. The source.multidot.drain interconnection layers are electrically connected to the source.multidot.drain regions through the conductive layers. One of the pair of conductive layers is formed in the same step as a bit line of a memory cell, by the same material as the bit line. The other one of the pair of conductive layers is formed in the same step as a storage node of a capacitor of the memory cell, by using the same material as the storage node. The pair of conductive layers prevent direct connection between the source.multidot.drain interconnection layer and the source.multidot.drain regions, so that reduction in size of the source.multidot.drain regions can be realized.
摘要翻译：包括在DRAM的外围电路中的MOS晶体管具有用于在一对源极引线区域的各个表面上互连的导电层。源极引线互连层通过导电层电连接到源极引线区域。通过与位线相同的材料，在与存储单元的位线相同的步骤中形成一对导电层。一对导电层中的另一个通过使用与存储节点相同的材料在与存储单元的电容器的存储节点相同的步骤中形成。一对导电层防止源极间隙互连层和源极引线区域之间的直接连接，从而可以实现源极引线区域的尺寸的减小。

44. 发明授权

US5659191A DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof 失效
标题翻译：具有通过利用衬垫层使MOS晶体管的源极 - 漏极互连接触小的外围电路的DRAM及其制造方法
公开(公告)号：US5659191A
公开(公告)日：1997-08-19
申请号：US456331
申请日：1995-06-01
申请人： Hideaki Arima
发明人： Hideaki Arima
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10852 , H01L27/105 , H01L27/10817 , Y10S257/903
摘要： A MOS transistor included in a peripheral circuit of a DRAM has conductive layers for interconnection on respective surfaces of a pair of source.multidot.drain regions. The source.multidot.drain interconnection layers are electrically connected to the source.multidot.drain regions through the conductive layers. One of the pair of conductive layers is formed in the same step as a bit line of a memory cell, by the same material as the bit line. The other one of the pair of conductive layers is formed in the same step as a storage node of a capacitor of the memory cell, by using the same material as the storage node. The pair of conductive layers prevent direct connection between the source.multidot.drain interconnection layer and the source.multidot.drain regions, so that reduction in size of the source.multidot.drain regions can be realized.
摘要翻译：包括在DRAM的外围电路中的MOS晶体管具有用于在一对源极引线区域的各个表面上互连的导电层。源极引线互连层通过导电层电连接到源极引线区域。通过与位线相同的材料，在与存储单元的位线相同的步骤中形成一对导电层。一对导电层中的另一个通过使用与存储节点相同的材料在与存储单元的电容器的存储节点相同的步骤中形成。一对导电层防止源极间隙互连层和源极引线区域之间的直接连接，从而可以实现源极引线区域的尺寸的减小。

45. 发明授权

US5612241A Method of manufacturing a DRAM having peripheral circuitry in which source drain interconnection contact of a MOS transistor is made small by utilizing a pad layer 失效
标题翻译：制造具有外围电路的DRAM的方法，其中通过利用衬垫层使MOS晶体管的源极漏极互连接点变小
公开(公告)号：US5612241A
公开(公告)日：1997-03-18
申请号：US558584
申请日：1995-10-31
申请人： Hideaki Arima
发明人： Hideaki Arima
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/105 , H01L27/10817 , Y10S257/903
摘要： A MOS transistor included in a peripheral circuit of a DRAM has conductive layers for interconnection on respective surfaces of a pair of source.multidot.drain regions. The source.multidot.drain interconnection layers are electrically connected to the source.multidot.drain regions through the conductive layers. One of the pair of conductive layers is formed in the same step as a bit line of a memory cell, by the same material as the bit line. The other one of the pair of conductive layers is formed in the same step as a storage node of a capacitor of the memory cell, by using the same material as the storage node. The pair of conductive layers prevent direct connection between the source.multidot.drain interconnection layer and the source.multidot.drain regions, so that reduction in size of the source.multidot.drain regions can be realized.
摘要翻译：包括在DRAM的外围电路中的MOS晶体管具有用于在一对源极引线区域的各个表面上互连的导电层。源极引线互连层通过导电层电连接到源极引线区域。通过与位线相同的材料，在与存储单元的位线相同的步骤中形成一对导电层。一对导电层中的另一个通过使用与存储节点相同的材料在与存储单元的电容器的存储节点相同的步骤中形成。一对导电层防止源极间隙互连层和源极引线区域之间的直接连接，从而可以实现源极引线区域的尺寸的减小。

46. 发明授权

US5428239A Semiconductor device having retrograde well and diffusion-type well 失效
标题翻译：具有逆行井和扩散型的半导体器件
公开(公告)号：US5428239A
公开(公告)日：1995-06-27
申请号：US71023
申请日：1993-06-03
申请人： Yoshinori Okumura , Tomonori Okudaira , Hideaki Arima
发明人： Yoshinori Okumura , Tomonori Okudaira , Hideaki Arima
IPC分类号： H01L27/10 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/105 , H01L27/108
CPC分类号： H01L21/823892 , H01L21/76221 , H01L21/823493 , H01L27/10805 , H01L27/0928 , H01L27/105
摘要： A DRAM is formed on a silicon substrate having a retrograde well and a diffusion-type well. The retrograde well has an impurity concentration profile which is set in steps by a plurality of ion-implantations. The diffusion-type well has an impurity concentration profile which changes monotonously by a thermal diffusion. A memory cell array is formed in the retrograde well region. A peripheral circuit is formed in the diffusion-type well region. The retrograde well enhances integration of devices included in the memory cell array. The diffusion-type well enhances the characteristic of insulating isolation between devices.
摘要翻译：在具有逆行阱和扩散型阱的硅衬底上形成DRAM。逆行井具有通过多个离子注入步骤设置的杂质浓度分布。扩散型阱具有通过热扩散单调变化的杂质浓度分布。在逆行井区域中形成记忆单元阵列。在扩散型阱区域中形成外围电路。逆行井增强了存储单元阵列中包含的器件的集成。扩散型井增强了器件之间绝缘隔离的特性。

47. 发明授权

US5404042A Semiconductor memory device having a plurality of well regions of different conductivities 失效
标题翻译：具有多个具有不同电导率的阱区的半导体存储器件
公开(公告)号：US5404042A
公开(公告)日：1995-04-04
申请号：US71925
申请日：1993-06-04
申请人： Yoshinori Okumura , Tomonori Okudaira , Hideaki Arima
发明人： Yoshinori Okumura , Tomonori Okudaira , Hideaki Arima
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/02 , H01L27/105 , H01L27/108 , H01L49/00 , H01L29/68 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/0218 , H01L27/105
摘要： A semiconductor memory device in accordance with the present invention includes a plurality of n well regions and p well regions in a p type silicon substrate. One of the p well regions is connected to an external power supply. Peripheries of the p well region having a memory cell array formed therein are surrounded by an n well region having a potential held at a positive potential. The n well region held at the positive potential prevents electrons introduced into the substrate due to undershoot from entering into a p well region through the p well region connected to the external power supply.
摘要翻译：根据本发明的半导体存储器件包括p型硅衬底中的多个n阱区和p阱区。 p个阱区中的一个连接到外部电源。具有其中形成有存储单元阵列的p阱区的周边被具有保持在正电位的电位的n阱区围绕。保持在正电位的n阱区防止由于下冲通过连接到外部电源的p阱区进入p阱区而引入到衬底中的电子。

48. 发明授权

US5381365A Dynamic random access memory having stacked type capacitor and manufacturing method therefor 失效
标题翻译：具有层叠型电容器的动态随机存取存储器及其制造方法
公开(公告)号：US5381365A
公开(公告)日：1995-01-10
申请号：US91675
申请日：1993-06-30
申请人： Natsuo Ajika , Hideaki Arima , Atsushi Hachisuka
发明人： Natsuo Ajika , Hideaki Arima , Atsushi Hachisuka
IPC分类号： H01L27/108 , H01L29/68 , H01L27/10
CPC分类号： H01L27/10817
摘要： The DRAM according to the present invention comprises so-called cylindrical stacked type capacitors. Each of the cylindrical stacked type capacitors comprises a base portion extending flat on an insulation layer and a surface of a substrate, and a cylindrical portion extending vertically and upwardly from the base portion. Then, the cylindrical portion vertically and upwardly protrudes from an outermost peripheral position of the base portion. As a result, an area where electrodes of the capacitor and capacitance of the capacitor can be increased. Furthermore, with a bit line located below an electrode layer of the capacitor, adjacent capacitors above the bit line can be isolated. Accordingly, it is possible to prevent the bit line contact from defining an isolation distance between the capacitors. Furthermore, an isolating layer patterned by etching is used as an isolating region between the capacitors and a lower electrode of the capacitor is formed along a surface of the isolating layer to form an isolation region between the adjacent capacitors. In addition, the lower electrode of the cylindrical stacked type capacitor is integrally formed by using a step formed in the insulation layer. As a result, the manufacturing step is simplified.
摘要翻译：根据本发明的DRAM包括所谓的圆柱形堆叠型电容器。每个圆柱形堆叠型电容器包括在绝缘层和基板的表面上平坦延伸的基部，以及从基部垂直和向上延伸的圆柱形部分。然后，圆筒部从基部的最外周位置向上方突出。结果，可以增加电容器的电极和电容器的电容的区域。此外，通过位于电容器的电极层下方的位线，可以隔离位线上方的相邻电容器。因此，可以防止位线接触限定电容器之间的隔离距离。此外，通过蚀刻图案化的隔离层用作电容器之间的隔离区域，并且电容器的下电极沿着隔离层的表面形成，以在相邻的电容器之间形成隔离区域。此外，圆柱形堆叠型电容器的下电极通过使用形成在绝缘层中的台阶整体地形成。结果，简化了制造步骤。

49. 发明授权

US5315140A Semiconductor device having a polysilicon capacitor with large grain diameter 失效
标题翻译：具有晶粒直径大的多晶硅电容器的半导体装置
公开(公告)号：US5315140A
公开(公告)日：1994-05-24
申请号：US8020
申请日：1993-01-22
申请人： Kazuyuki Sugahara , Hideaki Arima
发明人： Kazuyuki Sugahara , Hideaki Arima
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/16 , H01L29/94
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91 , H01L29/16 , H01L29/94
摘要： A semiconductor device includes a capacitor with an insulator having an improved durability. In the semiconductor device, a capacitor lower electrode 11 of the cylindrical capacitor includes a standing wall portion 11b which is formed of a polysilicon layer having a large crystal grain diameter (1000.ANG.-10000.ANG.).
摘要翻译：半导体器件包括具有改善的耐久性的具有绝缘体的电容器。在半导体装置中，圆筒形电容器的电容器下电极11包括由具有大晶粒直径（1000安格姆-10000昂贵）的多晶硅层形成的立壁部分11b。

50. 发明授权

US5229314A Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation 失效
标题翻译：具有其中具有锥形侧壁绝缘体的多层互连层的场效应晶体管的方法
公开(公告)号：US5229314A
公开(公告)日：1993-07-20
申请号：US925153
申请日：1992-08-06
申请人： Tomonori Okudaira , Hideaki Arima , Makoto Ohi , Kaoru Motonami , Yasushi Matsui
发明人： Tomonori Okudaira , Hideaki Arima , Makoto Ohi , Kaoru Motonami , Yasushi Matsui
IPC分类号： H01L27/108 , H01L29/417 , H01L29/78
CPC分类号： H01L29/41775 , H01L27/10817 , H01L29/7831
摘要： A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.
摘要翻译：公开了一种场效应晶体管及其制造方法，即使在缩小到更高的集成度时，也不会降低多层互连层之间的耐电压特性。该场效应晶体管包括形成在位线15两侧的侧壁21a，使得底侧端接触栅电极4b和4c的侧壁20a的上表面。插入在栅电极4b和4c之间的绝缘膜的厚度和形成电容器的低电极11的基部11a的厚度不降低。即使缩放到更高的集成度，耐压电压的特性也不会在多层互连层之间劣化。

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