专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US06307796B1 Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US06307796B1
公开(公告)日：2001-10-23
申请号：US09688083
申请日：2000-10-16
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C8/12 , G11C11/401 , G11C11/4087 , G11C29/50
摘要： A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.
摘要翻译：动态随机存取存储器包括以行和列排列的多个动态存储单元，连接到同一行上的存储单元的字线，连接到同一列上的存储单元的位线，字线选择电路，响应于内部地址信号，字线驱动电压源，字线驱动电路选择任意一行的字线选择功能，具有连接在字线驱动电压源和字线，用于响应于字线选择电路的输出信号驱动字线;以及控制电路，用于响应于从外部输入的电压应力测试控制信号，控制字线驱动电路，使得字线路驱动电路在接收到外部地址信号时，比在正常操作模式中选择的字线更多地驱动字线。

42. 再颁专利

USRE37184E1 Semiconductor memory and screening test method thereof 失效
标题翻译：半导体存储器及其筛选试验方法
公开(公告)号：USRE37184E1
公开(公告)日：2001-05-22
申请号：US09108266
申请日：1998-07-01
申请人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
发明人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
IPC分类号： G11C700
CPC分类号： G11C29/025 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C2029/5004 , G11C2029/5006
摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.
摘要翻译：半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线，线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据的存储单元阵列到相关位线上。

43. 发明授权

US06166975A Dynamic random access memory 失效
公开(公告)号：US06166975A
公开(公告)日：2000-12-26
申请号：US468314
申请日：1999-12-21
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G01R31/28 , G01R31/30 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C8/12 , G11C11/401 , G11C11/4087 , G11C29/50
摘要： A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.

44. 发明授权

US5659507A Clock synchronous type DRAM with data latch 失效
标题翻译：具有数据锁存器的时钟同步型DRAM
公开(公告)号：US5659507A
公开(公告)日：1997-08-19
申请号：US753432
申请日：1996-11-25
申请人： Tomoaki Yabe , Kenji Numata , Katsuhiko Sato , Ryo Haga , Shinji Miyano , Tohru Furuyama
发明人： Tomoaki Yabe , Kenji Numata , Katsuhiko Sato , Ryo Haga , Shinji Miyano , Tohru Furuyama
IPC分类号： G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1072 , G11C7/1078
摘要： A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate. The write circuit writes data into the data latch in synchronism with a clock signal. At the time of writing data into the memory cells, data is previously supplied to the data latch by the write circuit and latched in the data latch, and after the transfer gate control circuit controls the transfer gate to supply data to the bit line pairs from the data latch, the sense amplifier control circuit activates the sense amplifier.
摘要翻译：半导体存储器件包括存储单元阵列，行解码器，位线对，读出放大器，读出放大器控制电路，数据锁存器，传输门，传输门控制电路和写电路。存储单元阵列具有以阵列形式排列的动态存储单元。行解码器解码行地址信号以选择存储单元阵列的所需行中的一行。每个位线对连接到布置在存储单元阵列的相应列上的存储单元的每一个。读出放大器放大在配对位线上读出的数据，并将数据反馈给配对的位线以保存数据。读出放大器控制电路控制读出放大器的工作。数据锁存器锁存读出数据和写入数据。传输门在数据锁存器和读出放大器之间传送数据。传输门控制电路控制传输门。写入电路与时钟信号同步地将数据写入数据锁存器。在将数据写入存储器单元时，数据预先由写入电路提供给数据锁存器并锁存在数据锁存器中，并且在传输门控制电路控制传输门以向位线对提供数据之后数据锁存器，读出放大器控制电路激活读出放大器。

45. 发明授权

US5444652A Semiconductor memory device having a memory cell unit including a plurality of transistors connected in series 失效
标题翻译：具有包括串联连接的多个晶体管的存储单元的半导体存储器件
公开(公告)号：US5444652A
公开(公告)日：1995-08-22
申请号：US191301
申请日：1994-02-03
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/405 , G06F12/08 , G11C7/10 , G11C11/401 , G11C11/404 , G11C11/4091 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C11/24
CPC分类号： G11C7/106 , G06F12/0893 , G11C11/404 , G11C11/4091 , G11C11/4096 , G11C7/1051
摘要： A semiconductor memory device includes a memory cell array having a plurality of dynamic memory cells each of which has a plurality of cascade-connected MOS transistors and data storing capacitors each connected at one end to one end of a corresponding one of the MOS transistors, registers each provided for a corresponding one of columns of the memory cell array, for temporarily storing data time-sequentially read out from the memory cell; and switching elements for controlling the respective registers to be accessed independently from the memory cell array.
摘要翻译：半导体存储器件包括具有多个动态存储单元的存储单元阵列，每个动态存储单元具有多个级联连接的MOS晶体管和数据存储电容器，每个电容器的一端连接到相应的一个MOS晶体管的一端，寄存器每个提供用于存储单元阵列的列的相应一列，用于临时存储从存储单元时间顺序读出的数据; 以及用于控制要独立于存储单元阵列访问的相应寄存器的开关元件。

46. 发明授权

US5432733A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5432733A
公开(公告)日：1995-07-11
申请号：US201089
申请日：1994-02-24
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/405 , G06F12/08 , G11C7/10 , G11C11/401 , G11C11/404 , G11C11/4091 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C11/24
CPC分类号： G11C7/106 , G06F12/0893 , G11C11/404 , G11C11/4091 , G11C11/4096 , G11C7/1051
摘要： A semiconductor memory device includes a memory cell array having a plurality of dynamic memory cells each of which has a plurality of cascade-connected MOS transistors and data storing capacitors each connected at one end to one end of a corresponding one of the MOS transistors, registers each provided for a corresponding one of columns of the memory cell array, for temporarily storing data time-sequentially read out from the memory cell; and switching elements for controlling the respective registers to be accessed independently from the memory cell array.
摘要翻译：半导体存储器件包括具有多个动态存储单元的存储单元阵列，每个动态存储单元具有多个级联连接的MOS晶体管和数据存储电容器，每个电容器的一端连接到相应的一个MOS晶体管的一端，寄存器每个提供用于存储单元阵列的列的相应一列，用于临时存储从存储单元时间顺序读出的数据; 以及用于控制要独立于存储单元阵列访问的相应寄存器的开关元件。

47. 发明授权

US5386127A Semiconductor device having groups of pads which receive the same signal 失效
标题翻译：具有接收相同信号的焊盘组的半导体器件
公开(公告)号：US5386127A
公开(公告)日：1995-01-31
申请号：US248536
申请日：1994-05-24
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： H01L21/66 , G11C5/00 , H01L21/822 , H01L27/04 , H01L27/02
CPC分类号： G11C5/06 , G11C29/006 , G11C29/1201 , G11C29/48 , G11C5/00 , G11C5/066 , G11C7/1078 , G11C7/1084 , G11C7/109
摘要： A semiconductor device comprises a bonding pad serving as a power supply terminal and a plurality of bonding pads having the same function and serving as one of grouped terminals other than the power supply terminal.
摘要翻译：半导体器件包括用作电源端子的焊盘和具有与电源端子不同的分组端子之一具有相同功能的多个焊盘。

48. 发明授权

US5369612A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5369612A
公开(公告)日：1994-11-29
申请号：US172742
申请日：1993-12-27
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： H01L27/108 , G11C11/405 , G11C11/56 , H01L21/8242 , G11C7/02
CPC分类号： G11C11/565
摘要： A semiconductor memory device comprising a memory cell array having a plurality of dynamic memory cells, each of the memory cells including a plurality of MOS transistors connected by cascade connection, capacitors for storing data each having an end connected to an end of a corresponding one of the MOS transistors, and a register arranged in a column portion of the memory cell array, for temporarily registering the data read from the memory cells in a time series manner.
摘要翻译：一种半导体存储器件，包括具有多个动态存储单元的存储单元阵列，每个存储单元包括通过级联连接的多个MOS晶体管，用于存储数据的电容器，每个存储单元的端部连接到相应的一个 MOS晶体管和布置在存储单元阵列的列部分中的寄存器，用于以时间序列方式临时登记从存储器单元读取的数据。

49. 发明授权

US5343430A Method and circuitry for screening a dynamic memory device for defective circuits 失效
标题翻译：用于屏蔽有缺陷电路的动态存储器件的方法和电路
公开(公告)号：US5343430A
公开(公告)日：1994-08-30
申请号：US695014
申请日：1991-05-03
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G01R31/26 , G11C11/401 , G11C11/406 , G11C29/06 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00 , G11C29/00
CPC分类号： G11C11/406
摘要： A dynamic memory device includes a refresh counter, a row circuit, and a column AV5VpVcircuit. The dynamic memory device has a screening refresh mode for activating a circuit block in response to a signal other than a refresh address signal externally supplied, the circuit block including a refresh counter, row circuit, and column circuit.
摘要翻译：动态存储器件包括刷新计数器，行电路和列AV5VpVcircuit。动态存储装置具有响应于外部提供的刷新地址信号以外的信号来激活电路块的屏幕刷新模式，该电路块包括刷新计数器，行电路和列电路。

50. 发明授权

US5341326A Semiconductor memory having memory cell units each including cascade-connected MOS transistors 失效
标题翻译：具有各自包括级联连接的MOS晶体管的存储单元单元的半导体存储器
公开(公告)号：US5341326A
公开(公告)日：1994-08-23
申请号：US833045
申请日：1992-02-10
申请人： Satoru Takase , Natsuki Kushiyama , Tohru Furuyama
发明人： Satoru Takase , Natsuki Kushiyama , Tohru Furuyama
IPC分类号： G11C11/405 , G11C11/56 , H01L21/8242 , H01L27/108 , G11C11/24 , G11C11/34
CPC分类号： G11C11/565
摘要： A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors and having one end connected to a first node, and a plurality of capacitors for data storage connected at one end to the MOS transistors, respectively at the end remote from the node, and there is a predetermined regulation in relation of the capacitance of the capacitors.
摘要翻译：半导体存储单元包括级联栅极，其包括多个级联连接的MOS晶体管，并且其一端连接到第一节点;以及多个用于数据存储的电容器，其一端连接到MOS晶体管，分别在远离节点，并且存在关于电容器的电容的预定调节。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式