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    • 43. 发明授权
    • Semiconductor device having a controllable voltage supply
    • 具有可控电压源的半导体器件
    • US5706242A
    • 1998-01-06
    • US697508
    • 1996-08-26
    • Hiroshige HiranoToshiyuki Honda
    • Hiroshige HiranoToshiyuki Honda
    • G11C5/14G11C7/06G11C16/26G05F1/40
    • G11C7/067G11C16/26G11C5/143G11C2207/063
    • A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be a higher response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.
    • 半导体器件包括非易失性存储单元和电流检测型读出放大器,用于检测流过存储单元的数据线的电流。 半导体器件还设置有用于当检测到的电源电压超过设定值时输出第一电压检测信号并在检测到的电源电压未超过设定值时输出第二电压检测信号的元件。 感测放大器包括用于在电源电压上切换电平感测电流的相关特性以对第一电压检测信号作出较高响应的元件。 因此,可以避免在应用低电源电压下可能导致来自存储单元的数据的错误读取。
    • 45. 发明授权
    • Nonvolatile memory device, access device, and nonvolatile memory system
    • 非易失性存储器件,存取器件和非易失性存储器系统
    • US08661186B2
    • 2014-02-25
    • US12374672
    • 2007-07-26
    • Takuji MaedaToshiyuki HondaMasahiro NakanishiTadashi OnoTatsuya AdachiIsao Kato
    • Takuji MaedaToshiyuki HondaMasahiro NakanishiTadashi OnoTatsuya AdachiIsao Kato
    • G11C16/10G06F12/02G06F3/06
    • G06F3/0664G06F3/0605G06F3/061G06F3/0679G06F12/0246
    • An access device 100 includes an access speed information part 112 for informing an access speed required for data recording by the access device 100 to a nonvolatile memory device 200. The nonvolatile memory device includes an access condition determination part 212 for determining an access condition required for meeting the informed access speed and an access area determination unit 213 for determining an access area according to the determined access condition. The access device 100 informs the required access speed to the nonvolatile memory device 200 in advance so that the access condition determination part 212 and the access area determination part 213 in the nonvolatile memory device 200 realize data recording which meets the access speed informed in advance upon the data recording. Thus, it is possible to access all the nonvolatile memory devices at a desired speed regardless of difference in characteristics of the recording speed of each of the nonvolatile memory devices.
    • 访问装置100包括访问速度信息部分112,用于将访问装置100的数据记录所需的访问速度通知给非易失性存储装置200.非易失性存储装置包括访问条件确定部分212,用于确定访问条件 满足通知访问速度的访问区域确定单元213,用于根据确定的访问条件确定访问区域。 访问装置100预先向非易失性存储装置200通知所需的访问速度,使得非易失性存储装置200中的访问条件确定部212和访问区域确定部213实现满足预先通知的访问速度的数据记录 数据记录。 因此,无论每个非易失性存储器件的记录速度的特性差如何,都可以以所需的速度访问所有非易失性存储器件。
    • 49. 发明授权
    • Image pickup apparatus and method of manufacturing the same
    • 摄像装置及其制造方法
    • US08009222B2
    • 2011-08-30
    • US11338856
    • 2006-01-25
    • Naoyuki WatanabeToshiyuki HondaNoboru Hayasaka
    • Naoyuki WatanabeToshiyuki HondaNoboru Hayasaka
    • H04N5/225H04N11/04
    • H04N5/2254
    • To provide an image pickup apparatus with excellent optical characteristics as well as high reliability and a method of manufacturing the same, capable of efficiently manufacturing the image pickup apparatus in large quantities. The image pickup apparatus of the present invention includes a support board 10, an image pickup device 20 mounted on the support board 10, and a lens component 30 provided on the light receiving region of the image pickup device 20, wherein the lens component 30 has a protrusion part 33 provided around the lens part 31, and the height of the protrusion part 33 from the surface of image pickup device 20 is greater than that of the top 31A of lens part 31 from the surface of the image pickup device 20.
    • 为了提供具有优异的光学特性以及高可靠性的图像拾取装置及其制造方法,能够大量有效地制造图像拾取装置。 本发明的图像拾取装置包括支撑板10,安装在支撑板10上的图像拾取装置20和设置在图像拾取装置20的光接收区域上的透镜部件30,其中透镜部件30具有 设置在透镜部31周围的突出部33以及突出部33与摄像装置20的表面的高度大于透镜部31的顶面31A的从摄像装置20的表面的高度。
    • 50. 发明授权
    • Reduction of fragmentation in nonvolatile memory using alternate address mapping
    • 使用备用地址映射减少非易失性存储器中的碎片
    • US07877569B2
    • 2011-01-25
    • US11587808
    • 2005-04-28
    • Toshiyuki Honda
    • Toshiyuki Honda
    • G06F12/10
    • G06F3/0643G06F3/0607G06F3/0611G06F3/064G06F3/0679G06F11/2069G06F11/2087G06F12/0246G06F2212/7201G06F2212/7202
    • A nonvolatile storage device can read and write data by receiving a logical address from a host. The nonvolatile storage device includes: a nonvolatile memory writing and reading data based on a physical address; a logical/physical conversion table storing information on correspondence between the logical address and the physical address for each of a plurality of data management units; a duplication table storing information on correspondence between the logical address and the physical address of data arranged over a plurality of areas in a duplicate (redundant) manner in the nonvolatile memory and having a size smaller than a size of a data management unit; and a controller controlling an operation of the nonvolatile storage device. The controller permits duplicate (redundant) writing of data having a same logical address as the data (which has been written in one data management unit in another data management unit), and the controller performs a plurality of write modes for the duplicate (redundant) writing, and selectively switches between the write modes according to situation of a logical address change designated by the host.
    • 非易失性存储设备可以通过从主机接收逻辑地址来读写数据。 非易失性存储装置包括:非易失性存储器,基于物理地址写入和读取数据; 存储关于多个数据管理单元中的每一个的逻辑地址和物理地址之间的对应关系的信息的逻辑/物理转换表; 复制表,其存储关于在非易失性存储器中以复制(冗余)方式布置在多个区域上的数据的逻辑地址和物理地址之间的对应关系的信息,并且具有小于数据管理单元的大小的尺寸; 以及控制非易失性存储装置的操作的控制器。 控制器允许与具有相同逻辑地址的数据进行重复(冗余)写入,该数据已被写入另一个数据管理单元中的一个数据管理单元中,并且控制器执行多个写入模式用于复制(冗余) 根据由主机指定的逻辑地址变化的情况,在写入模式之间选择性地切换。