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    • 43. 发明授权
    • Structure and method of a column redundancy memory
    • 列冗余存储器的结构和方法
    • US06327197B1
    • 2001-12-04
    • US09660534
    • 2000-09-13
    • Juhan KimHing Wong
    • Juhan KimHing Wong
    • G11C700
    • G11C29/808
    • A memory architecture is disclosed that employs multiple column redundancies which provide multiple options for replacing a defective global odd or even bit line. Each column memory has two multiplexers, one for selecting a global odd bit line and another for selecting a global even bit line. Two or more column redundancies are coupled to each of the multiplexer in the column memory. In a first embodiment, the global odd and even bit lines are connected through odd and even sense amps in a regular column. In a second embodiment, the global odd bit line in a regular column connects through odd sense amps, while the global even bit line in the regular column connects through even sense amps. In a third embodiment, two or more sets of redundancy columns are commonly coupled to a left adjacent regular column and a right adjacent regular column.
    • 公开了一种采用多列冗余的存储器架构,其提供用于替换有缺陷的全局奇数或偶数位线的多个选项。 每列存储器具有两个多路复用器,一个用于选择全局奇数位线,另一个用于选择全局偶数位线。 两列或更多列冗余被耦合到列存储器中的多路复用器中的每一个。 在第一实施例中,全局奇数和偶数位线通过常规列中的奇数和偶数感测放大器连接。 在第二实施例中,常规列中的全局奇数位线通过奇数检测放大器连接,而常规列中的全局偶数位线通过均匀感测放大器连接。 在第三实施例中,两组或多组冗余列通常耦合到左相邻规则列和右相邻常规列。
    • 44. 发明授权
    • Parallel test circuit and method for wide input/output DRAM
    • 用于宽输入/输出DRAM的并行测试电路和方法
    • US06262928B1
    • 2001-07-17
    • US09661165
    • 2000-09-13
    • Juhan KimHing Wong
    • Juhan KimHing Wong
    • G11C2900
    • G11C29/02G11C29/34
    • The present invention discloses a parallel test circuit and method for testing even bit line and odd bit line in a memory block simultaneously. The parallel test circuit comprises an even test circuit for testing an even bit line and an odd test circuit for testing an odd bit line. The parallel test circuit also includes a write circuit for writing data to a bit line, a read circuit including a data sense amp, an output buffer, and a comparator. Furthermore, the present invention provides the capability to conduct disturbance test in neighboring even and odd cells.
    • 本发明公开了一种用于同时测试存储块中偶数位线和奇数位线的并行测试电路和方法。 并联测试电路包括用于测试偶数位线的偶数测试电路和用于测试奇数位线的奇数测试电路。 并行测试电路还包括用于将数据写入位线的写入电路,包括数据读出放大器,输出缓冲器和比较器的读取电路。 此外,本发明提供了在相邻偶数和奇数单元中进行干扰测试的能力。