会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Structure and method of a column redundancy memory
    • 列冗余存储器的结构和方法
    • US06327197B1
    • 2001-12-04
    • US09660534
    • 2000-09-13
    • Juhan KimHing Wong
    • Juhan KimHing Wong
    • G11C700
    • G11C29/808
    • A memory architecture is disclosed that employs multiple column redundancies which provide multiple options for replacing a defective global odd or even bit line. Each column memory has two multiplexers, one for selecting a global odd bit line and another for selecting a global even bit line. Two or more column redundancies are coupled to each of the multiplexer in the column memory. In a first embodiment, the global odd and even bit lines are connected through odd and even sense amps in a regular column. In a second embodiment, the global odd bit line in a regular column connects through odd sense amps, while the global even bit line in the regular column connects through even sense amps. In a third embodiment, two or more sets of redundancy columns are commonly coupled to a left adjacent regular column and a right adjacent regular column.
    • 公开了一种采用多列冗余的存储器架构,其提供用于替换有缺陷的全局奇数或偶数位线的多个选项。 每列存储器具有两个多路复用器,一个用于选择全局奇数位线,另一个用于选择全局偶数位线。 两列或更多列冗余被耦合到列存储器中的多路复用器中的每一个。 在第一实施例中,全局奇数和偶数位线通过常规列中的奇数和偶数感测放大器连接。 在第二实施例中,常规列中的全局奇数位线通过奇数检测放大器连接,而常规列中的全局偶数位线通过均匀感测放大器连接。 在第三实施例中,两组或多组冗余列通常耦合到左相邻规则列和右相邻常规列。
    • 2. 发明授权
    • Parallel test circuit and method for wide input/output DRAM
    • 用于宽输入/输出DRAM的并行测试电路和方法
    • US06262928B1
    • 2001-07-17
    • US09661165
    • 2000-09-13
    • Juhan KimHing Wong
    • Juhan KimHing Wong
    • G11C2900
    • G11C29/02G11C29/34
    • The present invention discloses a parallel test circuit and method for testing even bit line and odd bit line in a memory block simultaneously. The parallel test circuit comprises an even test circuit for testing an even bit line and an odd test circuit for testing an odd bit line. The parallel test circuit also includes a write circuit for writing data to a bit line, a read circuit including a data sense amp, an output buffer, and a comparator. Furthermore, the present invention provides the capability to conduct disturbance test in neighboring even and odd cells.
    • 本发明公开了一种用于同时测试存储块中偶数位线和奇数位线的并行测试电路和方法。 并联测试电路包括用于测试偶数位线的偶数测试电路和用于测试奇数位线的奇数测试电路。 并行测试电路还包括用于将数据写入位线的写入电路,包括数据读出放大器,输出缓冲器和比较器的读取电路。 此外,本发明提供了在相邻偶数和奇数单元中进行干扰测试的能力。
    • 5. 发明授权
    • Row redundancy block architecture
    • 行冗余块架构
    • US5691946A
    • 1997-11-25
    • US758783
    • 1996-12-03
    • John DeBrosseToshiaki KirihataHing Wong
    • John DeBrosseToshiaki KirihataHing Wong
    • G11C11/401G11C29/00G11C29/04H01L21/8242H01L27/108G11C5/06
    • G11C29/80G11C29/808G11C29/84
    • Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.
    • 有效减少设计空间的行冗余控制电路与字方向平行排列,并配置在冗余块的底部。 通过引入(1)与本地行冗余线共享的分裂全局总线,(2)半长度单向行冗余字线使能信号线,可以有效地布置冗余控制块 这允许节省空间,以及(3)分布式字线使能解码器被设计为利用节省的空间。 由地址与时序偏差引起的非法正常/冗余访问问题也已解决。 通过使用其相邻的冗余匹配检测在本地给出该检测所需的定时。 这允许电路作为地址驱动电路完全操作,导致快速可靠的冗余匹配检测。 此外,通过使用行冗余匹配检测来生成采样字线使能信号(SWLE)。 一个双输入或门允许SWLE设置采样字线(SWL)的时间与字线使能(WLE)信号设置字线(WL)的时间相同。 无论模式如何,SWLE设置SWL的时间保持一致,从而消除了现有的可靠性问题。 该双输入OR门与行冗余匹配检测相结合,可作为理想的采样字线使能发生器。