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41. 发明授权

US08263468B2 Thin body semiconductor devices 有权
标题翻译：薄体半导体器件
公开(公告)号：US08263468B2
公开(公告)日：2012-09-11
申请号：US12766859
申请日：2010-04-24
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/66742 , H01L29/66772 , H01L29/66795 , H01L29/78696
摘要： A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.
摘要翻译：公开了一种用于制造FET器件的方法。该方法包括在绝缘体上提供主体，其中主体具有适于承载设备通道的至少一个表面。选择身体为Si，Ge或其合金混合物。选择体层小于临界厚度，其临界厚度定义为在高温加工过程中聚集的厚度。这种临界厚度对于平面器件可以是约4nm，对于非平面器件而言约8nm。该方法还包括在低温下清除氧的表面，并且通过选择性外延形成凸起的源极/漏极，同时使用清除的表面进行接种。在氧的表面清除之后，并且在选择性外延之前，防止了清除的表面的氧曝光。

42. 发明授权

US08759200B2 Methods and apparatus for selective epitaxy of Si-containing materials and substitutionally doped crystalline Si-containing material 有权
标题翻译：含Si材料和替代掺杂结晶含Si材料的选择性外延的方法和装置
公开(公告)号：US08759200B2
公开(公告)日：2014-06-24
申请号：US13135031
申请日：2011-06-23
申请人： Terry Arthur Francis , Satoshi Hasaka , Paul David Brabant , Robert Torres, Jr. , Hong He , Alexander Reznicek , Thomas N. Adam , Devendra K. Sadana
发明人： Terry Arthur Francis , Satoshi Hasaka , Paul David Brabant , Robert Torres, Jr. , Hong He , Alexander Reznicek , Thomas N. Adam , Devendra K. Sadana
IPC分类号： H01L21/205
CPC分类号： H01L21/02532 , C23C16/30 , C23C16/325 , C30B25/02 , C30B29/06 , H01L21/0237 , H01L21/02529 , H01L21/02573 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636
摘要： The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550° C. and a pressure in the range of about 10 mTorr-200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.
摘要翻译：本发明公开了在改进的化学气相沉积（mCVD）条件下，外延硅膜可以通过将包含在腔室内的衬底暴露于相对高的载气流量与在较低的硅前体流速小于约550℃，压力范围为约10mTorr-200Torr。此外，通过在改进的CVD条件下使用四硅烷作为硅源和含碳气体如十二烷基甲基环己硅烷或四甲基二硅烷以相对高的流速进行沉积，可以将晶体Si原位掺杂以含有相对高水平的取代碳。

43. 发明申请

US20130040438A1 EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 审中-公开
标题翻译：首先使用HCl / GeH4 / H2SiCl2表面清洁的外延工艺
公开(公告)号：US20130040438A1
公开(公告)日：2013-02-14
申请号：US13206248
申请日：2011-08-09
申请人： Thomas N. Adam , Hong He , Alexander Reznicek , Devendra K. Sadana , Paul D. Brabant , Keith Chung , Manabu Shinriki
发明人： Thomas N. Adam , Hong He , Alexander Reznicek , Devendra K. Sadana , Paul D. Brabant , Keith Chung , Manabu Shinriki
IPC分类号： H01L21/205 , H01L21/322
CPC分类号： H01L21/0237 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/02661
摘要： A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.
摘要翻译：一种沉积外延层的方法，包括化学清洗半导体衬底的沉积表面，并在预烘烤温度下用含氢气体处理半导体衬底的沉积表面。含氢气体处理可以在外延沉积室中进行。含氢气体从半导体衬底的沉积表面去除含氧材料。然后可以用包含至少一种盐酸（HCl），锗烷（GeH4）和二氯硅烷（H 2 SiCl 2））的气流来处理半导体衬底的沉积表面，该气流随着温度从预烘烤温度达到外延沉积温度。可以将至少一种源气体施加到沉积表面，用于材料层的外延沉积。

44. 发明申请

US20130040440A1 EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 审中-公开
公开(公告)号：US20130040440A1
公开(公告)日：2013-02-14
申请号：US13613003
申请日：2012-09-13
申请人： Thomas N. Adam , Hong He , Alexander Reznicek , Devendra K. Sadana , Paul D. Brabant , Keith Chung , Manabu Shinriki
发明人： Thomas N. Adam , Hong He , Alexander Reznicek , Devendra K. Sadana , Paul D. Brabant , Keith Chung , Manabu Shinriki
IPC分类号： H01L21/20
CPC分类号： H01L21/0237 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/02661
摘要： A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.

45. 发明授权

US07329596B2 Method for tuning epitaxial growth by interfacial doping and structure including same 有权
标题翻译：通过界面掺杂和包括其的结构来调谐外延生长的方法
公开(公告)号：US07329596B2
公开(公告)日：2008-02-12
申请号：US11259654
申请日：2005-10-26
申请人： Katherina E. Babich , Bruce B. Doris , David R. Medeiros , Devendra K. Sadana
发明人： Katherina E. Babich , Bruce B. Doris , David R. Medeiros , Devendra K. Sadana
IPC分类号： H01L21/44
CPC分类号： H01L29/0847 , H01L21/2236 , H01L21/2256 , H01L21/26513 , H01L21/823418 , H01L21/823814 , H01L29/66628 , H01L29/7834
摘要： A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces. More specifically, the invention comprises a method for counterdoping of n-FET and/or p-FET regions of silicon circuitry during the halo and/or extension implantation process utilizing a technique by which the surface characteristics of the two regions are made similar with respect to their response to wet or dry surface preparation and which renders the two previously dissimilar surfaces amenable to simultaneous epitaxial growth of raised source/drain structures; but not otherwise affecting the electrical performance of the resulting device.
摘要翻译：允许通过新颖的表面制备方案不使衬底变薄的不同掺杂的半导体表面（n型和p型）上的半导体材料均匀地同时外延生长的方法，以及由提供了将该方案实现为集成电路的过程集成流程。本发明的方法可以用于从不同的表面进行半导体材料的选择性或非选择性外延生长。更具体地说，本发明包括一种在卤素和/或延伸注入过程期间用于对硅电路的n-FET和/或p-FET区进行反掺杂的方法，利用这样的技术，使两个区域的表面特性相对于它们对湿表面或干表面制备的反应，并且使得两个先前不同的表面可以容易地升高的源极/漏极结构的同时外延生长; 但不会影响所得设备的电气性能。

46. 发明授权

US07790593B2 Method for tuning epitaxial growth by interfacial doping and structure including same 失效
标题翻译：通过界面掺杂和包括其的结构来调谐外延生长的方法
公开(公告)号：US07790593B2
公开(公告)日：2010-09-07
申请号：US11962796
申请日：2007-12-21
申请人： Katherina E. Babich , Bruce B. Doris , David R. Medeiros , Devendra K. Sadana
发明人： Katherina E. Babich , Bruce B. Doris , David R. Medeiros , Devendra K. Sadana
IPC分类号： H01L21/44
CPC分类号： H01L29/0847 , H01L21/2236 , H01L21/2256 , H01L21/26513 , H01L21/823418 , H01L21/823814 , H01L29/66628 , H01L29/7834
摘要： A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces. More specifically, the invention comprises a method for counterdoping of n-FET and/or p-FET regions of silicon circuitry during the halo and/or extension implantation process utilizing a technique by which the surface characteristics of the two regions are made similar with respect to their response to wet or dry surface preparation and which renders the two previously dissimilar surfaces amenable to simultaneous epitaxial growth of raised source/drain structures; but not otherwise affecting the electrical performance of the resulting device.
摘要翻译：允许通过新颖的表面制备方案不使衬底变薄的不同掺杂的半导体表面（n型和p型）上的半导体材料均匀地同时外延生长的方法，以及由提供了将该方案实现为集成电路的过程集成流程。本发明的方法可以用于从不同的表面进行半导体材料的选择性或非选择性外延生长。更具体地说，本发明包括一种在卤素和/或延伸注入过程期间用于对硅电路的n-FET和/或p-FET区进行反掺杂的方法，利用这样的技术，使两个区域的表面特性相对于它们对湿表面或干表面制备的反应，并且使得两个先前不同的表面可以容易地升高的源极/漏极结构的同时外延生长; 但不会影响所得设备的电气性能。

47. 发明申请

US20080153270A1 METHOD FOR TUNING EPITAXIAL GROWTH BY INTERFACIAL DOPING AND STRUCTURE INCLUDING SAME 失效
公开(公告)号：US20080153270A1
公开(公告)日：2008-06-26
申请号：US11962796
申请日：2007-12-21
申请人： Katherina E. Babich , Bruce B. Doris , David R. Medeiros , Devendra K. Sadana
发明人： Katherina E. Babich , Bruce B. Doris , David R. Medeiros , Devendra K. Sadana
IPC分类号： H01L21/22
CPC分类号： H01L29/0847 , H01L21/2236 , H01L21/2256 , H01L21/26513 , H01L21/823418 , H01L21/823814 , H01L29/66628 , H01L29/7834
摘要： A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces. More specifically, the invention comprises a method for counterdoping of n-FET and/or p-FET regions of silicon circuitry during the halo and/or extension implantation process utilizing a technique by which the surface characteristics of the two regions are made similar with respect to their response to wet or dry surface preparation and which renders the two previously dissimilar surfaces amenable to simultaneous epitaxial growth of raised source/drain structures; but not otherwise affecting the electrical performance of the resulting device.

48. 发明授权

US10396229B2 Solar cell with interdigitated back contacts formed from high and low work-function-tuned silicides of the same metal 有权
公开(公告)号：US10396229B2
公开(公告)日：2019-08-27
申请号：US13103583
申请日：2011-05-09
申请人： Joel P. De Souza , Harold J. Hovel , Daniel A. Inns , Jeehwan Kim , Christian Lavoie , Devendra K. Sadana , Katherine L. Saenger , Davood Shahrjerdi , Zhen Zhang
发明人： Joel P. De Souza , Harold J. Hovel , Daniel A. Inns , Jeehwan Kim , Christian Lavoie , Devendra K. Sadana , Katherine L. Saenger , Davood Shahrjerdi , Zhen Zhang
IPC分类号： H01L31/07 , H01L31/0224 , H01L31/18 , H01L31/068
摘要： A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.

49. 发明授权

US09059245B2 Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides 有权
标题翻译：具有超薄SOI层和掩埋氧化物的绝缘体上半导体（SOI）衬底
公开(公告)号：US09059245B2
公开(公告)日：2015-06-16
申请号：US13483781
申请日：2012-05-30
申请人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76243
摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.
摘要翻译：提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

50. 发明申请

US20130320483A1 SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES 有权
标题翻译：半导体绝缘体（SOI）衬底，具有超薄SOI层和铜氧化物
公开(公告)号：US20130320483A1
公开(公告)日：2013-12-05
申请号：US13483781
申请日：2012-05-30
申请人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/762 , H01L29/02
CPC分类号： H01L21/76243
摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.
摘要翻译：提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

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