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41. 发明授权

US06563745B1 Memory device and method for dynamic bit inversion 有权
标题翻译：用于动态位反转的存储器件和方法
公开(公告)号：US06563745B1
公开(公告)日：2003-05-13
申请号：US10023466
申请日：2001-12-14
申请人： Alper Ilkbahar
发明人： Alper Ilkbahar
IPC分类号： G11C1604
CPC分类号： G11C16/10
摘要： A memory device and method for storing bits in a memory array is provided. In one preferred embodiment, a memory device is provided comprising a plurality of memory cells that are in a first digital state and can be switched to a second digital state. A plurality of bits to be stored in the memory array are provided, and if the plurality of bits comprise more bits in the second digital state than in the first digital state, the plurality of bits are inverted before being stored in the memory array. In another preferred embodiment, a memory device is provided comprising a memory array and bit inversion circuitry. In yet another preferred embodiment, a plurality of bits are inverted before being stored in a memory array if the plurality of bits comprise more bits in a non-preferred digital state than in a preferred digital state.
摘要翻译：提供了一种用于存储存储器阵列中的位的存储器件和方法。在一个优选实施例中，提供一种存储器件，其包括处于第一数字状态并可被切换到第二数字状态的多个存储器单元。提供要存储在存储器阵列中的多个比特，并且如果多个比特在第二数字状态中比在第一数字状态中包含更多的比特，则在被存储在存储器阵列中之前，多个比特被反转。在另一优选实施例中，提供了一种包括存储器阵列和位反转电路的存储器件。在另一个优选实施例中，如果多个位在非优选数字状态中比在优选数字状态中包含更多位，则在存储在存储器阵列中之前将多个位反转。

42. 发明授权

US6154845A Power failure safe computer architecture 有权
标题翻译：电源故障安全计算机架构
公开(公告)号：US6154845A
公开(公告)日：2000-11-28
申请号：US151484
申请日：1998-09-11
申请人： Alper Ilkbahar , Christopher Cheng
发明人： Alper Ilkbahar , Christopher Cheng
IPC分类号： G06F1/26 , G06F1/30 , G06F11/00
CPC分类号： G06F11/0754 , G06F1/26 , G06F1/30 , G06F11/0724 , G06F11/00 , G06F11/004
摘要： A component powered by a first power supply activates a driving signal. The driving signal indicates that both a second power supply voltage has a magnitude greater than a reference voltage and an enable signal is active. A driver transfers the output signal when the driving signal is active. In a multi-processor computer system implementation, each of two processor cores are independently supplied power by each of two core power supplies while a single I/O power supply supplies power to the I/O rings of both processors. Each processor includes a bus isolation circuit to prevent its respective processor from loading the system bus in the event that a core power supply fails.
摘要翻译：由第一电源供电的部件激活驱动信号。驱动信号指示第二电源电压都具有大于参考电压的幅度，并且使能信号有效。当驱动信号有效时，驱动器传输输出信号。在多处理器计算机系统实现中，两个处理器核心中的每一个由两个核心电源中的每一个独立供电，而单个I / O电源为两个处理器的I / O环供电。每个处理器包括总线隔离电路，以防止其核心电源故障的情况下其各自的处理器加载系统总线。

43. 发明授权

US6031385A Method and apparatus for testing compensated buffer circuits 失效
标题翻译：用于测试补偿缓冲电路的方法和装置
公开(公告)号：US6031385A
公开(公告)日：2000-02-29
申请号：US823215
申请日：1997-03-24
申请人： Alper Ilkbahar
发明人： Alper Ilkbahar
IPC分类号： G01R31/30 , G01R31/317 , G01R31/28
CPC分类号： G01R31/30 , G01R31/31715 , G01R31/31723
摘要： A method and an apparatus for testing compensated input/output buffers. In one embodiment, a compensated input/output buffer includes a node from which a plurality of compensation devices are coupled in parallel to a particular voltage level, such as for example V.sub.CC or ground. Compensation control signals are received by each one of the compensation devices such that the compensation signals are configured to selectively switch on and off each one of the plurality of compensation devices. An input/output test bus is coupled to the node and thus has access to each one of the compensation devices. Test circuitry is configured to selectively switch on and off each one of the compensation devices such that a switchable conductive path is formed from the node to the particular potential level through each one of the plurality of compensation devices. By observing the switchable conductive paths through each respective compensation device from the input/output test bus, proper functionality of the compensation devices in the compensated input/output buffer is verified.
摘要翻译：用于测试补偿输入/输出缓冲器的方法和装置。在一个实施例中，经补偿的输入/输出缓冲器包括多个补偿装置并联耦合到特定电压电平（例如VCC或地）的节点。补偿控制信号由补偿装置中的每一个接收，使得补偿信号被配置为选择性地接通和关闭多个补偿装置中的每一个。输入/输出测试总线耦合到节点，从而可以访问每个补偿设备。测试电路被配置为选择性地打开和关闭每个补偿装置，使得通过多个补偿装置中的每一个从节点形成到特定电位电平的可切换导电路径。通过从输入/输出测试总线观察通过每个相应补偿装置的可切换导电路径，验证补偿输入/输出缓冲器中补偿装置的适当功能。

44. 发明授权

US5869983A Method and apparatus for controlling compensated buffers 失效
标题翻译：用于控制补偿缓冲器的方法和装置
公开(公告)号：US5869983A
公开(公告)日：1999-02-09
申请号：US823220
申请日：1997-03-24
申请人： Alper Ilkbahar , Stefan Rusu
发明人： Alper Ilkbahar , Stefan Rusu
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018585 , H03K19/0005
摘要： A method and an apparatus for controlling compensated buffer circuits. In one embodiment, a compensation buffer control circuit includes a compensation unit with a compensation signal memory location such as a compensation register. The compensation unit is configured to produce a local compensation control signal to control a compensated buffer circuit. The compensation signal memory location is configured to selectively receive and store and the local compensation control signal generated by the compensation unit. The contents of the compensation signal memory location may be read, which allows for the external reading of the local compensation signal generated by the compensation unit. In addition, an external write of an external compensation control signal may be performed to the compensation signal memory location such that the output of the compensation unit can be overridden. A compensated buffer circuit is coupled to selectively receive either the local compensation control signal or the external compensation control signal.
摘要翻译：一种用于控制补偿缓冲电路的方法和装置。在一个实施例中，补偿缓冲器控制电路包括具有诸如补偿寄存器的补偿信号存储器位置的补偿单元。补偿单元被配置为产生局部补偿控制信号以控制经补偿的缓冲电路。补偿信号存储器位置被配置为选择性地接收和存储由补偿单元产生的局部补偿控制信号。可以读取补偿信号存储器位置的内容，这允许由补偿单元产生的局部补偿信号的外部读取。此外，外部补偿控制信号的外部写入可以被执行到补偿信号存储器位置，使得可以覆盖补偿单元的输出。耦合补偿缓冲电路以有选择地接收局部补偿控制信号或外部补偿控制信号。

45. 发明授权

US08110476B2 Memory cell that includes a carbon-based memory element and methods of forming the same 有权
标题翻译：包含碳基记忆元件的记忆单元及其形成方法
公开(公告)号：US08110476B2
公开(公告)日：2012-02-07
申请号：US12418855
申请日：2009-04-06
申请人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Shricker
发明人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Shricker
IPC分类号： H01L21/00 , H01L21/06 , H01L29/02 , G11C11/00
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/0002 , G11C13/0009 , G11C13/025 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/285 , H01L51/0048 , Y10S977/712 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/734 , Y10S977/788 , Y10S977/789 , Y10S977/79 , Y10S977/855 , Y10S977/943
摘要： In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.
摘要翻译：根据本发明的方面，提供了一种形成存储单元的方法，所述方法包括在基板上形成操舵元件，以及形成耦合到所述操舵元件的存储元件，其中所述存储元件包括碳基材料具有不超过10个原子层的厚度。可以通过重复进行以下步骤来形成记忆元件：形成碳基材料层，该层具有约一个单层的厚度，并使碳基材料层进行热退火。还描述了其他方面。

46. 发明申请

US20090256132A1 MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME 有权
标题翻译：包含基于碳的存储元件的存储器单元及其形成方法
公开(公告)号：US20090256132A1
公开(公告)日：2009-10-15
申请号：US12418855
申请日：2009-04-06
申请人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
发明人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
IPC分类号： H01L47/00 , H01L21/365
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/0002 , G11C13/0009 , G11C13/025 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/285 , H01L51/0048 , Y10S977/712 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/734 , Y10S977/788 , Y10S977/789 , Y10S977/79 , Y10S977/855 , Y10S977/943
摘要： In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.
摘要翻译：根据本发明的方面，提供了一种形成存储单元的方法，所述方法包括在基板上形成操舵元件，以及形成耦合到所述操舵元件的存储元件，其中所述存储元件包括碳基材料具有不超过10个原子层的厚度。可以通过重复进行以下步骤来形成记忆元件：形成碳基材料层，该层具有约一个单层的厚度，并使碳基材料层进行热退火。还描述了其他方面。

47. 发明授权

US07505321B2 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same 有权
标题翻译：并联串联晶体管串的可编程存储器阵列结构及其制造和操作的方法
公开(公告)号：US07505321B2
公开(公告)日：2009-03-17
申请号：US10335078
申请日：2002-12-31
申请人： Roy E. Scheuerlein , Christopher Petti , Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov
发明人： Roy E. Scheuerlein , Christopher Petti , Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06 , G11C8/00
CPC分类号： H01L27/11568 , G11C11/5621 , G11C16/0483 , H01L27/115 , H01L27/1159
摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.
摘要翻译：三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F2存储单元布局。可以仅使用隧穿电流对存储器阵列进行编程和擦除，并且不通过未选择的存储器单元形成泄漏路径。每个NAND串包括用于分别将NAND串的一端耦合到全局位线的两个块选择器件，另一端连接到共享偏置节点。块内的一对NAND串共享相同的全局位线。存储器单元优选地是耗尽型SONOS器件，块选择器件也是如此。存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。多个层上的NAND串可以连接到单个层上的全局位线。通过在每个存储器级别交错NAND串并且每个块使用两个共享偏置节点，对于NAND串的每一端的开关器件需要非常少的附加开销。不同存储器级别的NAND串优选通过垂直堆叠的通孔连接在一起，每个优选地连接到多于一个的存储器级。每个存储器级别可以以每级别少于三个掩码来生成。

48. 发明申请

US20070263423A1 THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED ARRAY LINE MEMORY ARRAY 有权
标题翻译：配有SEGMENTED阵列线记忆阵列的三维存储器件
公开(公告)号：US20070263423A1
公开(公告)日：2007-11-15
申请号：US11764789
申请日：2007-06-18
申请人： Roy Scheuerlein , Alper Ilkbahar , Luca Fasoli
发明人： Roy Scheuerlein , Alper Ilkbahar , Luca Fasoli
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。在某些EEPROM实施例中，该阵列包括多层分段位线，其中多层具有段连接开关，并且共享与全局位线层的垂直连接。这样的存储器阵列可以通过对于半选择的存储器单元的更少的写入干扰效应来实现，并且可以用要被擦除的小得多的单元块来实现。

49. 发明授权

US07233024B2 Three-dimensional memory device incorporating segmented bit line memory array 有权
标题翻译：结合分段位线存储器阵列的三维存储器件
公开(公告)号：US07233024B2
公开(公告)日：2007-06-19
申请号：US10403752
申请日：2003-03-31
申请人： Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli
发明人： Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli
IPC分类号： H01L27/10
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。在某些EEPROM实施例中，该阵列包括多层分段位线，其中多层具有段连接开关，并且共享与全局位线层的垂直连接。这样的存储器阵列可以通过对于半选择的存储器单元的更少的写入干扰效应来实现，并且可以用要被擦除的小得多的单元块来实现。

50. 发明授权

US07219271B2 Memory device and method for redundancy/self-repair 有权
标题翻译：用于冗余/自修复的存储器件和方法
公开(公告)号：US07219271B2
公开(公告)日：2007-05-15
申请号：US10024646
申请日：2001-12-14
申请人： Bendik Kleveland , Alper Ilkbahar , Roy E. Scheuerlein
发明人： Bendik Kleveland , Alper Ilkbahar , Roy E. Scheuerlein
IPC分类号： G11C29/00 , G11C17/00
CPC分类号： G11C29/72 , G11C29/4401 , G11C29/80
摘要： The preferred embodiments described herein provide a memory device and method for redundancy/self-repair. In one preferred embodiment, a memory device is provided comprising a primary block of memory cells and a redundant block of memory cells. In response to an error in writing to the primary block, a flag is stored in a set of memory cells allocated to the primary block, and the redundant block is written into. In another preferred embodiment, an error in writing to a primary block is detected while an attempt is made to write to that block. In response to the error, the redundant block is written into. In yet another preferred embodiment, a memory device is provided comprising a three-dimensional memory array and redundancy circuitry. In still another preferred embodiment, a method for testing a memory array is provided. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
摘要翻译：本文所述的优选实施例提供了用于冗余/自修复的存储器件和方法。在一个优选实施例中，提供存储器件，其包括存储器单元的主块和存储器单元的冗余块。响应于对主块的写入错误，标志被存储在分配给主块的一组存储器单元中，并且冗余块被写入。在另一优选实施例中，在尝试写入该块时检测到写入主块的错误。响应错误，冗余块被写入。在另一优选实施例中，提供了包括三维存储器阵列和冗余电路的存储器件。在又一优选实施例中，提供了一种用于测试存储器阵列的方法。提供了其它优选实施方案，并且本文所述的各优选实施方案可以单独使用或彼此组合使用。

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