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41. 发明授权

US07982244B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07982244B2
公开(公告)日：2011-07-19
申请号：US12553496
申请日：2009-09-03
申请人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
发明人： Atsuhiro Sato , Hiroyuki Nitta , Fumitaka Arai
IPC分类号： H01L29/68 , H01L29/417 , H01L27/105
CPC分类号： H01L27/11524 , H01L21/76816 , H01L27/11521
摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.
摘要翻译：半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

42. 发明申请

US20110069524A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110069524A1
公开(公告)日：2011-03-24
申请号：US12821585
申请日：2010-06-23
申请人： Takayuki TOBA , Hiroyuki Nitta
发明人： Takayuki TOBA , Hiroyuki Nitta
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C8/14 , G11C13/0007 , G11C13/004 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/72
摘要： A semiconductor memory device includes a control circuit. The control circuit applies a first voltage to a selected one of a upper interconnections, applies a second voltage to an unselected one of the upper interconnections, applies a third voltage to a first dummy upper interconnection and independently controls the first to third voltages to be set to different values.
摘要翻译：半导体存储器件包括控制电路。控制电路将第一电压施加到上部互连中的所选择的一个中，将第二电压施加到未选择的上部互连中的一个，将第三电压施加到第一虚拟上部互连并独立地控制要设置的第一至第三电压到不同的值。

43. 发明申请

US20070140036A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20070140036A1
公开(公告)日：2007-06-21
申请号：US11678632
申请日：2007-02-26
申请人： Mitsuhiro NOGUCHI , Akira Goda , Hiroyuki Nitta
发明人： Mitsuhiro NOGUCHI , Akira Goda , Hiroyuki Nitta
IPC分类号： G11C7/00
CPC分类号： G06F11/1008 , G06F11/108 , G11C7/22 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C29/50004 , G11C29/52 , G11C29/76 , G11C29/82 , G11C29/84 , G11C2029/0409 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.
摘要翻译：半导体存储器件包括：存储单元阵列，具有彼此平行布置的多个数据选择线;多个数据传输线，彼此并联设置，以与数据选择线相交;以及布置的电可重写存储器单元在数据选择线和数据传输线之间的交叉部分; 用于驱动存储单元阵列的数据选择线的数据选择线驱动器; 连接到存储单元阵列的数据传输线的读出放大器电路，用于对数据选择线之一选择的存储器单元执行数据读取; 以及用于对存储单元阵列的数据读取进行定时控制的控制电路，用于根据存储单元阵列的选定数据区输出不同的至少两种类型的定时信号。

44. 发明申请

US20060263958A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：US20060263958A1
公开(公告)日：2006-11-23
申请号：US11419079
申请日：2006-05-18
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroyuki Nitta
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Hiroyuki Nitta
IPC分类号： H01L21/337
CPC分类号： H01L27/088 , H01L21/823857 , H01L21/823892 , H01L27/0207 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed.

45. 再颁专利

USRE39366E1 Liquid crystal driver and liquid crystal display device using the same 有权
公开(公告)号：USRE39366E1
公开(公告)日：2006-10-31
申请号：US09324168
申请日：1999-06-02
申请人： Hiroyuki Nitta , Hiroyuki Mano , Tsutomu Furuhashi , Isao Takita , Satoru Tsunekawa , Toshio Futami , Makiko Ikeda
发明人： Hiroyuki Nitta , Hiroyuki Mano , Tsutomu Furuhashi , Isao Takita , Satoru Tsunekawa , Toshio Futami , Makiko Ikeda
IPC分类号： G09G3/36
CPC分类号： G09G3/2011 , G09G3/3614 , G09G3/3655 , G09G3/3688 , G09G3/3696 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0297 , G09G2330/023
摘要： A liquid crystal driver includes a voltage generator for generating gray scale voltages on the basis of reference voltages, and an output device for selecting one gray scale voltage from the generated gray scale voltages in accordance with display data, for applying inversion/non-inversion control to the selected gray scale voltage with respect to an inversion reference voltage on the basis of the selected gray scale voltage, an AC switching signal and the inversion reference voltage, and for outputting different liquid crystal supply voltages for one and the same display data to a liquid crystal panel.

46. 发明授权

US07113163B2 Liquid crystal display apparatus 有权
公开(公告)号：US07113163B2
公开(公告)日：2006-09-26
申请号：US09888641
申请日：2001-06-26
申请人： Hiroyuki Nitta , Takeshi Maeda , Kazuyoshi Kawabe , Junichi Hirakata
发明人： Hiroyuki Nitta , Takeshi Maeda , Kazuyoshi Kawabe , Junichi Hirakata
IPC分类号： G09G3/36
CPC分类号： G09G3/342 , G02F1/133604 , G02F2001/133612 , G09G3/2011 , G09G3/2018 , G09G3/2077 , G09G3/3648 , G09G2310/024 , G09G2310/08 , G09G2320/0252 , G09G2320/0257 , G09G2320/0261 , G09G2320/062 , G09G2320/0633 , G09G2320/064 , G09G2320/0673 , G09G2320/103 , G09G2340/16 , G09G2360/16
摘要： The present invention includes a panel on which a plurality of pixels are located, a light-source for visualizing an image displayed on the plurality of pixels, a controlling circuit for controlling the light-source, and an image-signal tone characteristic controlling circuit. Moreover, the light-source controlling circuit has a function of repeating a period. Here, the period includes a 1st time-period during which an electric current having a 1st intensity is fed to the light-source, and a 2nd time-period during which an electric current having a 2nd intensity differing from the 1st intensity is fed to the light-source. The light-source controlling circuit controls the 1st time-period and the 2nd time-period in accordance with display information. Also, in accordance with the display information as well, the tone characteristic controlling circuit is controlled so that the excellent contrast will be always available.

47. 发明申请

US20060092113A1 Display device and driving method thereof 审中-公开
公开(公告)号：US20060092113A1
公开(公告)日：2006-05-04
申请号：US11300305
申请日：2005-12-15
申请人： Hiroyuki Nitta , Nobuyuki Koganezawa , Nobuhiro Takeda , Tsutomu Furuhashi , Masashi Nakamura
发明人： Hiroyuki Nitta , Nobuyuki Koganezawa , Nobuhiro Takeda , Tsutomu Furuhashi , Masashi Nakamura
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G2310/0205 , G09G2310/061 , G09G2320/0261
摘要： A hold-type display device for eliminating blurring without damaging the display brightness of moving images. The display device includes a pixel array including a plurality of pixels, a plurality of first signal lines, a plurality of second signal lines, a first driving circuit outputting scanning signals to the plurality of first signal lines, and a second driving circuit outputting display signals to the plurality of second signal lines. The first driving circuit repeats a step for sequentially selecting the first signal lines every Y lines for every N times and a step for selecting the first signal lines every Z lines for every M times which follows the N times. The second driving circuit repeats outputting N times the display signals and outputting M times a blanking signal which masks an image displayed on corresponding pixels.

48. 发明申请

US20050206002A1 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same 失效
标题翻译：具有镶嵌结构的布线层的半导体器件及其制造方法
公开(公告)号：US20050206002A1
公开(公告)日：2005-09-22
申请号：US11121976
申请日：2005-05-05
申请人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
发明人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
IPC分类号： H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/532 , H01L27/108 , H01L21/4763 , H01L23/48
CPC分类号： H01L21/76846 , H01L21/32134 , H01L21/7682 , H01L21/76843 , H01L21/76862 , H01L21/76865 , H01L21/76897 , H01L23/5222 , H01L23/5329 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.
摘要翻译：在半导体器件中，在设置在半导体衬底上的氧化硅膜的表面部分中形成布线图案槽。布线层被埋入布线图案槽中，其间插入阻挡金属膜。从布线图形槽的各侧壁部选择性地去除阻挡金属膜。换句话说，阻挡金属膜仅留在布线图案槽的底部。因此，可以在半导体器件中形成具有在布线图案槽的每个侧壁和布线层的每一侧之间的介电常数低的中空部的镶嵌布线层。

49. 发明授权

US06906419B2 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same 失效
公开(公告)号：US06906419B2
公开(公告)日：2005-06-14
申请号：US09883210
申请日：2001-06-19
申请人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
发明人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
IPC分类号： H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/532 , H01L27/108 , H01L29/76 , H01L29/00
CPC分类号： H01L21/76846 , H01L21/32134 , H01L21/7682 , H01L21/76843 , H01L21/76862 , H01L21/76865 , H01L21/76897 , H01L23/5222 , H01L23/5329 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

50. 发明授权

US06882592B2 Semiconductor memory device 失效
公开(公告)号：US06882592B2
公开(公告)日：2005-04-19
申请号：US10696028
申请日：2003-10-30
申请人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
发明人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
IPC分类号： G11C16/02 , G06F11/10 , G11C8/00 , G11C11/34 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/42 , G11C29/52 , H01L21/8247 , H01L27/00 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G06F11/1008 , G06F11/108 , G11C7/22 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C29/50004 , G11C29/52 , G11C29/76 , G11C29/82 , G11C29/84 , G11C2029/0409 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.

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