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41. 发明申请

US20100309724A1 SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE 有权
标题翻译：仅使用单通道晶体管将电压施加到选定字线的半导体存储器件
公开(公告)号：US20100309724A1
公开(公告)日：2010-12-09
申请号：US12856962
申请日：2010-08-16
申请人： Hiroshi Nakamura , Kenichi Imamiya
发明人： Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/3459 , H01L27/115
摘要： A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.
摘要翻译：半导体存储器件具有存储单元阵列，第一导电类型的第一晶体管，第二导电类型的第二晶体管和第一导电类型的第三晶体管。第一晶体管的源极或漏极连接到每条字线。第二晶体管的漏极连接到第一晶体管的栅极。第三晶体管的源极连接到第一晶体管的栅极。第二晶体管和第三晶体管的栅极不连接，第二晶体管的源极不连接到第三晶体管的漏极，并且第二晶体管的栅极和第三晶体管的漏极具有不同的电压电平彼此相反的逻辑水平。

42. 发明申请

US20100309723A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD 有权
公开(公告)号：US20100309723A1
公开(公告)日：2010-12-09
申请号：US12855507
申请日：2010-08-12
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

43. 发明授权

US07787277B2 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
标题翻译：半导体存储器件能够实现具有高操作可靠性和高产量的芯片
公开(公告)号：US07787277B2
公开(公告)日：2010-08-31
申请号：US12052882
申请日：2008-03-21
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.
摘要翻译：提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部并且将第二块布置在其另一部分上。存储单元阵列的端侧上的第一存储单元单元的结构与第二存储单元单元的结构不同。用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

44. 发明授权

US07783237B2 Developing blade 失效
标题翻译：开发刀片
公开(公告)号：US07783237B2
公开(公告)日：2010-08-24
申请号：US12281150
申请日：2007-05-18
申请人： Shinji Souma , Hiroshi Nakamura
发明人： Shinji Souma , Hiroshi Nakamura
IPC分类号： G03G15/08
CPC分类号： G03G15/0812 , C08G77/04 , C08K3/04 , C08K3/041 , C08K3/045 , C08L23/04 , C08L83/04 , G03G2215/0634 , Y02P20/123 , C08L2666/06 , C08L2666/04
摘要： The blade member of the invention is composed mainly of silicone rubber and contains as an additive component at least one selected from the group consisting of ultra-high molecular-weight-polyethylene, carbon nanotube, and fullerene. It is thus possible to decrease the coefficient of friction of silicone rubber in a practical range and without detrimental to its flexibility or other physical properties to let the developing blade slip off more, thereby diminishing the amount of abrasion of the rubber and improving on the robustness of the developing blade without detrimental to image quality. Decreasing the coefficient of friction to let the developing blade slip off more has additional advantages: a decrease in the force of contact of the developing blade with a developing roll, which contributes more to energy savings resulting from the size reductions of a driving motor, and making the developer equipment compact.
摘要翻译：本发明的叶片构件主要由硅橡胶构成，作为添加成分，含有选自超高分子量聚乙烯，碳纳米管和富勒烯中的至少一种。因此，可以在实用的范围内降低硅橡胶的摩擦系数，并且不会对其柔性或其他物理性质产生不利影响，从而使显影刮板脱落更多，从而减少橡胶的磨损量并提高其坚固性的显影刀片，而不损害图像质量。降低摩擦系数以使显影刮板滑落更多具有另外的优点：显影刮板与显影辊的接触力降低，这对于由于驱动电机的尺寸减小而导致的能量节省更多;以及使开发设备紧凑。

45. 发明授权

US07768057B2 NAND-type EEPROM with increased reading speed 有权
标题翻译： NAND型EEPROM具有增加的读取速度
公开(公告)号：US07768057B2
公开(公告)日：2010-08-03
申请号：US11969740
申请日：2008-01-04
申请人： Hiroshi Nakamura , Kenichi Imamiya
发明人： Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： H01L29/94 , H01L23/62
CPC分类号： H01L27/11526 , G11C11/5621 , G11C16/0483 , G11C16/26 , H01L27/115 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.
摘要翻译：在由多个存储单元串联连接的NAND单元组成的EEPROM中，通过数据读取操作选择的块中的存储单元的控制栅极电压Vread与电压Vsg1，Vsg2 在所选择的块中选择晶体管的选择栅极，从而使得可以实现高速读取，而不会导致插入在选择栅极和选择晶体管的沟道之间的绝缘膜的击穿。如果使存储器单元的控制栅极电压与选择的电压不同，则也可以在DINOR单元，AND单元，NOR单元和与其连接的单个存储单元的NAND单元中实现高速读数。选择晶体管的栅极。

46. 发明授权

US07756599B2 Substrate processing apparatus, program for performing operation and control method thereof, and computer readable storage medium storing the program 有权
标题翻译：衬底处理装置，用于执行其操作和控制方法的程序以及存储程序的计算机可读存储介质
公开(公告)号：US07756599B2
公开(公告)日：2010-07-13
申请号：US11254668
申请日：2005-10-21
申请人： Tomoyuki Kudo , Jun Ozawa , Hiroshi Nakamura , Kazunori Kazama , Tsuyoshi Moriya , Hiroyuki Nakayama , Hiroshi Nagaike
发明人： Tomoyuki Kudo , Jun Ozawa , Hiroshi Nakamura , Kazunori Kazama , Tsuyoshi Moriya , Hiroyuki Nakayama , Hiroshi Nagaike
IPC分类号： G06F19/00 , B65H1/00 , H01L21/306
CPC分类号： H01L21/67201 , H01L21/67017 , H01L21/67253 , H01L21/67748 , Y10S414/135 , Y10S414/139
摘要： A computer readable storage medium storing a program for performing an operation method of a substrate processing apparatus is provided. The operation method includes the steps of introducing a nonreactive gas into the vacuum preparation chamber before the gate valve is opened while the substrate is transferred between the vacuum preparation chamber of the vacuum processing unit and the transfer unit, stopping introducing the nonreactive gas when an inner pressure of the vacuum preparation chamber becomes same as an atmospheric pressure, starting an evacuation process of the corrosive gas in the vacuum preparation chamber and then opening to atmosphere performed by letting the vacuum preparation chamber communicate with an atmosphere, and opening the gate valve after the step of opening to atmosphere.
摘要翻译：提供一种存储用于执行基板处理装置的操作方法的程序的计算机可读存储介质。操作方法包括以下步骤：在基板在真空处理单元的真空处理室和转印单元的真空准备室之间转移时，在闸阀打开之前将非反应性气体引入真空准备室中，当内部真空制备室的压力与大气压力相同，开始真空制备室中的腐蚀性气体的抽空处理，然后通过使真空制备室与大气连通而进入大气，并在真空准备室之后打开闸阀向大气开放的一步。

47. 发明授权

US07751259B2 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal 有权
公开(公告)号：US07751259B2
公开(公告)日：2010-07-06
申请号：US11904560
申请日：2007-09-27
申请人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C7/00
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

48. 发明申请

US20100061149A1 Non-Volatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20100061149A1
公开(公告)日：2010-03-11
申请号：US12621134
申请日：2009-11-18
申请人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
摘要翻译：非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中在预定的阈值电平范围内。在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于要存储在其中一个存储单元中的一位二电平数据。

49. 发明授权

US07672158B2 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control 有权
标题翻译：具有与选定字线相邻的未选择字线的非易失性半导体存储器件在不同的定时被充电用于程序干扰控制
公开(公告)号：US07672158B2
公开(公告)日：2010-03-02
申请号：US12048442
申请日：2008-03-14
申请人： Hiroshi Nakamura , Tomoharu Tanaka
发明人： Hiroshi Nakamura , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/30
摘要： A non-volatile semiconductor memory device comprises a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing.
摘要翻译：非易失性半导体存储器件包括数据可重写非易失性存储器单元的存储单元阵列或包含存储单元的存储单元单元，以及多个字线，每个字线共同连接到存储器中相同行上的存储器单元单元格阵列。在数据写入期间的写入脉冲施加中，写入用的高电压被施加到所选择的字线，并且用于写入的中间电压被施加到至少两个未被选择的字线。将位于所选择的字线和源极线之间的第一字线充电到用于写入的第一中间电压的开始之后，将位于所选择的字线和位线接触之间的第二字线开始充电到第二写入中间电压。

50. 发明授权

US07663967B2 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal 有权
标题翻译：具有多个芯片的半导体存储器件和输出忙信号的能力
公开(公告)号：US07663967B2
公开(公告)日：2010-02-16
申请号：US11973073
申请日：2007-10-05
申请人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C8/00
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.
摘要翻译：一个包装包含多个存储器芯片。每个存储器芯片具有产生忙信号的I / O端子。当电源电压值在上电序列之后达到指定和保证的范围时，忙信号使能忙状态。忙信号保持忙状态，直到完成多个存储器芯片的初始化操作。在完成多个存储器芯片的所有初始化操作之后，忙信号释放忙状态。

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