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41. 发明申请

US20110199825A1 NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非易失存储器件，其操作方法和包括其的存储器系统
公开(公告)号：US20110199825A1
公开(公告)日：2011-08-18
申请号：US13028918
申请日：2011-02-16
申请人： Jinman Han , Sunil Shim , Hansoo Kim , Jaehoon Jang , Byoungkeun Son
发明人： Jinman Han , Sunil Shim , Hansoo Kim , Jaehoon Jang , Byoungkeun Son
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/3418 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased.
摘要翻译：提供了一种操作包括基板的非易失性存储器件的方法和具有沿着垂直于衬底的方向堆叠的多个存储单元的存储器块。该方法包括：响应于所选择的子块的读取，从所选择的存储器块的子块中读取选定的子块的数据并选择刷新所选存储块的每个子块，其中所选存储块的每个子块被单独擦除。

42. 发明申请

US20140016408A1 NONVOLATILE MEMORY DEVICES HAVING VERTICALLY INTEGRATED NONVOLATILE MEMORY CELL SUB-STRINGS THEREIN 有权
标题翻译：具有垂直集成非易失性存储单元子带的非易失性存储器件
公开(公告)号：US20140016408A1
公开(公告)日：2014-01-16
申请号：US14024844
申请日：2013-09-12
申请人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
发明人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：根据本发明的实施例的非易失性存储器件包括高度集成的非易失性存储器单元的垂直堆叠。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

43. 发明授权

US08409977B2 Three-dimensional semiconductor memory device and a method of fabricating the same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US08409977B2
公开(公告)日：2013-04-02
申请号：US12858057
申请日：2010-08-17
申请人： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmi Hwang , Wonseok Cho , Jinsoo Lim
发明人： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmi Hwang , Wonseok Cho , Jinsoo Lim
IPC分类号： H01L21/8229
CPC分类号： H01L29/7926 , H01L27/11556 , H01L27/11582
摘要： A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer along surfaces of the plurality of recess regions, and forming a conductive pattern within each recess region.
摘要翻译：一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器层，并且形成导电体每个凹陷区域内的图案。

44. 发明申请

US20120003800A1 Methods of Forming Nonvolatile Memory Devices Having Vertically Integrated Nonvolatile Memory Cell Sub-Strings Therein and Nonvolatile Memory Devices Formed Thereby 有权
标题翻译：形成具有垂直集成的非易失性存储器单元子串的非易失性存储器件的方法及其形成的非易失性存储器件
公开(公告)号：US20120003800A1
公开(公告)日：2012-01-05
申请号：US13165576
申请日：2011-06-21
申请人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
发明人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： H01L21/8239
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

45. 发明申请

US20110287623A1 Three-Dimensional Nonvolatile Memory Devices Having Sub-Divided Active Bars and Methods of Manufacturing Such Devices 有权
标题翻译：具有子分割活动条的三维非易失性存储器件及其制造方法
公开(公告)号：US20110287623A1
公开(公告)日：2011-11-24
申请号：US13197026
申请日：2011-08-03
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L21/336
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

46. 发明授权

US08013389B2 Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices 有权
标题翻译：具有分割活动杆的三维非易失性存储器件及其制造方法
公开(公告)号：US08013389B2
公开(公告)日：2011-09-06
申请号：US12612125
申请日：2009-11-04
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L29/66
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

47. 发明申请

US20110115010A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20110115010A1
公开(公告)日：2011-05-19
申请号：US12943126
申请日：2010-11-10
申请人： Sunil Shim , Sunghoi Hur , Hansoo Kim , Jaehoon Jang , Hoosung Cho
发明人： Sunil Shim , Sunghoi Hur , Hansoo Kim , Jaehoon Jang , Hoosung Cho
IPC分类号： H01L27/11
CPC分类号： H01L21/02365 , H01L21/02697 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.
摘要翻译：提供一种三维半导体存储器件。三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。

48. 发明授权

US08873294B2 Nonvolatile memory devices, erasing methods thereof and memory systems including the same 有权
标题翻译：非易失性存储器件，其擦除方法和包括其的存储器系统
公开(公告)号：US08873294B2
公开(公告)日：2014-10-28
申请号：US13295335
申请日：2011-11-14
申请人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
发明人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
IPC分类号： G11C16/16 , G11C16/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , H01L29/792 , G11C16/30 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.
摘要翻译：提供了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。所述擦除方法包括将地电压施加到与所述电池串的地选择晶体管连接的接地选择线; 将接地电压施加到与电池串的选择晶体管连接的串选择线; 对与单元串的存储单元连接的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。

49. 发明授权

US08576629B2 Operating method of nonvolatile memory device 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US08576629B2
公开(公告)日：2013-11-05
申请号：US13315523
申请日：2011-12-09
申请人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
发明人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459 , H01L27/11582
摘要： Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括编程多个单元串中的第一选择晶体管并对多个单元串中的多个存储单元进行编程。对第一选择晶体管进行编程包括将第一电压提供给与待编程的第一选择晶体管连接的第一位线，以及将不同的第二电压提供给连接到第一选择晶体管的第二位线以被禁止编程; 接通多个单元串中的第二选择晶体管，并将第一编程电压提供给与第一选择晶体管连接的多个第一选择线中的所选择的第一选择线，以及将第三电压提供给未选择的第一选择线多个第一选择线。

50. 发明申请

US20130182502A1 Operating Methods of Nonvolatile Memory Devices 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US20130182502A1
公开(公告)日：2013-07-18
申请号：US13784969
申请日：2013-03-05
申请人： Byeong-in Cheo , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
发明人： Byeong-in Cheo , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
IPC分类号： G11C16/14 , G11C7/14
CPC分类号： G11C16/14 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Disclosed are methods of operating a nonvolatile memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the plurality of cell strings; floating ground selection lines connected to ground selection transistors of the plurality of cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。所述方法可以包括将字线擦除电压施加到连接到所述多个单元串的存储单元的字线; 连接到多个单元串的接地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。

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