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41. 发明授权

US07855422B2 Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process 有权
标题翻译：通过单个多晶硅工艺形成高电阻电阻器和高容量电容器
公开(公告)号：US07855422B2
公开(公告)日：2010-12-21
申请号：US11444852
申请日：2006-05-31
申请人： YongZhong Hu , Sung-Shan Tai
发明人： YongZhong Hu , Sung-Shan Tai
IPC分类号： H01L29/76
CPC分类号： H01L27/0629 , H01L28/20 , H01L28/60 , Y10S438/957
摘要： A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.
摘要翻译：半导体器件包括晶体管，电容器和电阻器，其中电容器包括用作底部导电层的掺杂多晶硅层，其中具有作为顶部导电的Ti / TiN层覆盖的电介质层的硅化物块（SAB）层从而构成单个多晶硅层金属 - 绝缘体 - 多晶硅（MIP）结构。虽然高片rho电阻也形成在同一个多晶硅层上，多晶硅层的差分掺杂。

42. 发明申请

US20080265289A1 Device structure and manufacturing method using HDP deposited source-body implant block 有权
标题翻译：使用HDP沉积源体植入块的装置结构和制造方法
公开(公告)号：US20080265289A1
公开(公告)日：2008-10-30
申请号：US11796985
申请日：2007-04-30
申请人： Anup Bhalla , Francios Hebert , Sung-Shan Tai , Sik K. Lui
发明人： Anup Bhalla , Francios Hebert , Sung-Shan Tai , Sik K. Lui
IPC分类号： H01L29/78 , H01L21/336 , H01L29/812 , H01L21/338
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
摘要翻译：本发明公开了一种半导体功率器件。沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域从而可以减少用于制造半导体功率器件的掩模。

43. 发明授权

US07256446B2 One time programmable memory cell 有权
标题翻译：一次可编程存储单元
公开(公告)号：US07256446B2
公开(公告)日：2007-08-14
申请号：US11122848
申请日：2005-05-05
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L29/788
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112 , H01L27/11206
摘要： This invention discloses a one-time programmable (OTP) memory cell. The OTP memory cell includes a dielectric layer disposed between two conductive polysilicon segments wherein the dielectric layer is ready to change from a non-conductive state to a conductive state through an induced voltage breakdown. In a preferred embodiment, one of the conductive polysilicon segments further includes an etch undercut configuration for conveniently inducing the voltage breakdown in the dielectric layer. In a preferred embodiment, the dielectric layer is further formed as sidewalls covering the edges and corners of a first polysilicon segments to conveniently induce a voltage breakdown in the dielectric layer by the edge and corner electrical field effects.
摘要翻译：本发明公开了一种可编程（OTP）存储单元。 OTP存储单元包括设置在两个导电多晶硅段之间的电介质层，其中介电层准备好通过感应电压击穿从非导电状态改变到导通状态。在优选实施例中，导电多晶硅段中的一个还包括蚀刻底切配置，用于方便地引起电介质层中的电压击穿。在优选实施例中，电介质层还被形成为覆盖第一多晶硅段的边缘和角部的侧壁，以便通过边缘和拐角电场效应方便地引起电介质层中的电压击穿。

44. 发明申请

US20070170498A1 Configuration and method to form mosfet devices with low resistance silicide gate and mesa contact regions 有权
标题翻译：用于形成具有低电阻硅化物栅极和台面接触区域的mosfet器件的配置和方法
公开(公告)号：US20070170498A1
公开(公告)日：2007-07-26
申请号：US11338019
申请日：2006-01-24
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.
摘要翻译：一种用于形成功率MOSFET的新型集成方案，特别是形成栅极和台面接触区域的杀螨剂，以及通过浸渍层使用多个能量接触植入物，以形成导电体接触物，其通过杀螨剂与源区域短接。

45. 发明授权

US10896968B2 Device structure and manufacturing method using HDP deposited source-body implant block 有权
公开(公告)号：US10896968B2
公开(公告)日：2021-01-19
申请号：US15499487
申请日：2017-04-27
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
IPC分类号： H01L29/423 , H01L29/06 , H01L29/40
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

46. 发明授权

US09024378B2 Device structure and manufacturing method using HDP deposited source-body implant block 有权
标题翻译：使用HDP沉积源体植入块的装置结构和制造方法
公开(公告)号：US09024378B2
公开(公告)日：2015-05-05
申请号：US13763644
申请日：2013-02-09
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K Lui
IPC分类号： H01L29/78 , H01L21/265 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/265 , H01L21/2652 , H01L21/26586 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
摘要翻译：本发明公开了一种半导体功率器件。沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域从而可以减少用于制造半导体功率器件的掩模。

47. 发明申请

US20140225187A1 DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK 审中-公开
标题翻译：使用HDP沉积源体植入块的装置结构和制造方法
公开(公告)号：US20140225187A1
公开(公告)日：2014-08-14
申请号：US13763644
申请日：2013-02-09
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
IPC分类号： H01L29/78 , H01L29/66 , H01L21/265
CPC分类号： H01L29/7827 , H01L21/265 , H01L21/2652 , H01L21/26586 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
摘要翻译：本发明公开了一种半导体功率器件。沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域从而可以减少用于制造半导体功率器件的掩模。

48. 发明申请

US20130175612A1 DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH 有权
标题翻译：具有通道停止电位器的双栅氧化物晶体管MOSFET
公开(公告)号：US20130175612A1
公开(公告)日：2013-07-11
申请号：US13780579
申请日：2013-02-28
申请人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
发明人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.
摘要翻译：公开了半导体器件和制造方法。该器件包括形成在位于半导体衬底的有源区中的沟槽中的多个栅电极。第一栅极流道形成在基板中并电连接到栅电极，其中第一栅极流道围绕有源区。第二浇口浇道连接到第一浇口浇道并且位于活性区域和终止区域之间。终端结构围绕第一和第二栅极流道和有源区域。端接结构包括在衬底中的绝缘体衬里的沟槽中的导电材料，其中端接结构电气短路到衬底的源极或体层，从而形成用于器件的通道停止。

49. 发明授权

US08236653B2 Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions 有权
标题翻译：用于形成具有低电阻硅化物栅极和台面接触区域的MOSFET器件的配置和方法
公开(公告)号：US08236653B2
公开(公告)日：2012-08-07
申请号：US13361950
申请日：2012-01-31
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicided layers for both gate contact regions and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicided layers.
摘要翻译：一种用于形成功率MOSFET的新颖的集成方案，特别是形成用于两个栅极接触区域和台面接触区域的浸渍层，以及使用多个能量接触植入物通过该水浸层形成导电体接触物，该接触体通过浸渍层。

50. 发明申请

US20120129306A1 CONFIGURATION AND METHOD TO FORM MOSFET DEVICES WITH LOW RESISTANCE SILICIDE GATE AND MESA CONTACT REGIONS 有权
标题翻译：形成具有低电阻硅胶门和MESA接触区域的MOSFET器件的配置和方法
公开(公告)号：US20120129306A1
公开(公告)日：2012-05-24
申请号：US13361950
申请日：2012-01-31
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicided layers for both gate contact regions and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicided layers.
摘要翻译：一种用于形成功率MOSFET的新颖的集成方案，特别是形成用于两个栅极接触区域和台面接触区域的浸渍层，以及使用多个能量接触植入物通过该水浸层形成导电体接触物，该接触体通过浸渍层。

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