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41. 发明授权

US07653855B2 Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device 有权
标题翻译：随机数测试电路，随机数生成电路，半导体集成电路，IC卡和信息终端设备
公开(公告)号：US07653855B2
公开(公告)日：2010-01-26
申请号：US11875360
申请日：2007-10-19
申请人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
发明人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F7/58 , G01R31/3181
摘要： A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.
摘要翻译：随机数测试电路包括：计数单元，用于对随机数序列中的特定值比特的重复次数进行计数，串联发生的重复;检测单元，用于检测与随机数中的比特种类对应的多个数字数字序列，以及基于该数字确定随机数序列是否正常的确定单元。

42. 发明申请

US20090222502A1 RANDOM NUMBER GENERATOR 有权
标题翻译：随机数发电机
公开(公告)号：US20090222502A1
公开(公告)日：2009-09-03
申请号：US12235995
申请日：2008-09-23
申请人： Kazutaka IKEGAMI , Shinichi Yasuda
发明人： Kazutaka IKEGAMI , Shinichi Yasuda
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： A random number generator includes: a variable frequency oscillator that includes: a selection circuit having multiple input terminals and an output terminal; a parallel circuit having an input terminal and multiple output terminals that are respectively connected to the input terminals of the selection circuit, the parallel circuit including one or more buffer circuits to be selected by the selection circuit; and an inverter circuit having a control terminal, the inverter circuit being connected to the input terminal of the parallel circuit and to the output terminal of the selection circuit; and a latch circuit connected to the variable frequency oscillator.
摘要翻译：随机数发生器包括：可变频率振荡器，包括：具有多个输入端子和输出端子的选择电路; 并联电路，其具有分别连接到选择电路的输入端子的输入端子和多个输出端子，并联电路包括由选择电路选择的一个或多个缓冲电路; 以及具有控制端子的逆变器电路，所述逆变器电路连接到所述并联电路的输入端子和所述选择电路的输出端子; 以及连接到可变频率振荡器的锁存电路。

43. 发明申请

US20090217222A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20090217222A1
公开(公告)日：2009-08-27
申请号：US12211842
申请日：2008-09-17
申请人： Shinichi Yasuda , Kumiko Nomura , Keiko Abe
发明人： Shinichi Yasuda , Kumiko Nomura , Keiko Abe
IPC分类号： G06F17/50
CPC分类号： G06F11/006 , G06F11/2242
摘要： A semiconductor integrated circuit includes: a plurality of processor elements each including a test circuit which tests whether there is a failure in the processor element and outputs a result of the test; a plurality of switch boxes provided so as to be respectively associated with processor elements, each of the switch boxes configured to have a table to store information of another processor element and transmit information of a corresponding processor element to the other processor element based on information stored in the table; a plurality of identification circuits provided so as to be respectively associated with processor elements, each of the identification circuits configured to identify a defective processor element on the basis of the result of the test and output location information of the defective processor element; and a transmission circuit configured to transmit the location information of the defective processor element output from the identification circuit to the switch boxes.
摘要翻译：半导体集成电路包括：多个处理器元件，每个处理器元件包括测试电路，该测试电路测试处理器元件中是否存在故障并输出测试结果; 设置为分别与处理器元件相关联的多个开关盒，每个开关盒被配置为具有用于存储另一个处理器元件的信息的表格，并且基于存储的信息将相应的处理器元件的信息发送到另一个处理器元件在桌子上设置为分别与处理器元件相关联的多个识别电路，每个识别电路被配置为基于测试的结果和缺陷处理器元件的输出位置信息来识别有缺陷的处理器元件; 以及发送电路，被配置为将从识别电路输出的缺陷处理器元件的位置信息发送到开关盒。

44. 发明申请

US20060023488A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060023488A1
公开(公告)日：2006-02-02
申请号：US11165404
申请日：2005-06-24
申请人： Shinichi Yasuda , Keiko Abe
发明人： Shinichi Yasuda , Keiko Abe
IPC分类号： G11C11/00
CPC分类号： G11C11/14
摘要： A semiconductor memory includes: a first node and a second node; a first MIS transistor, having first conductive carrier flows, including a source electrode connected to a first power supply, a drain electrode connected to the second node, and a gate electrode connected to the first node; a second MIS transistor, having second conductive carrier flows, including a source electrode connected to a second power supply, a drain electrode connected to the second node, and a gate electrode connected to the first node; and a resistance change element connected between the first node and the second node and having a variable resistance due to the direction in which a voltage is applied, wherein information is written in the resistance change element by applying a voltage between the first and the second node, and stored information is read out by applying a low or high input voltage to the first node and reading out a voltage difference in the second node.
摘要翻译：半导体存储器包括：第一节点和第二节点; 具有第一导电载流子的第一MIS晶体管，包括连接到第一电源的源电极，连接到第二节点的漏电极和连接到第一节点的栅电极; 具有第二导电载流子的第二MIS晶体管，包括连接到第二电源的源电极，连接到第二节点的漏电极和连接到第一节点的栅电极; 以及连接在第一节点和第二节点之间并且由于施加电压的方向而具有可变电阻的电阻变化元件，其中通过在第一和第二节点之间施加电压将信息写入电阻变化元件并且通过向第一节点施加低或高输入电压并读出第二节点中的电压差来读出存储的信息。

45. 发明申请

US20050108308A1 Random number generating circuit, semiconductor integrated circuit, IC card and information terminal device 有权
标题翻译：随机数发生电路，半导体集成电路，IC卡和信息终端装置
公开(公告)号：US20050108308A1
公开(公告)日：2005-05-19
申请号：US10919291
申请日：2004-08-17
申请人： Shinichi Yasuda , Shinobu Fujita
发明人： Shinichi Yasuda , Shinobu Fujita
IPC分类号： G06F7/58 , G09C1/00
CPC分类号： G06F7/58
摘要： A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.
摘要翻译：随机数产生电路接收以第一产生速率产生的第一数字随机数信号作为输出，产生第二数字随机数信号，该第二数字随机数信号的第二发生速率是第一发生速率的两倍。提供了包括随机数电路的半导体集成电路，IC卡和信息终端装置。

46. 发明授权

US4910270A Composition containing epoxy resin, di(meth)acrylate, N-heterocylic compound and polyamine 失效
标题翻译：含有环氧树脂，二（甲基）丙烯酸酯，N-杂环化合物和多胺的组合物
公开(公告)号：US4910270A
公开(公告)日：1990-03-20
申请号：US243044
申请日：1988-09-12
申请人： Zenichiro Maekawa , Kazuo Uede , Shinichi Yasuda , Tetsuzi Takata , Yosiaki Turuta
发明人： Zenichiro Maekawa , Kazuo Uede , Shinichi Yasuda , Tetsuzi Takata , Yosiaki Turuta
IPC分类号： B32B27/04 , C08F283/10 , C08G59/50 , C08G59/58 , C08J5/24
CPC分类号： C08J5/24 , B32B27/04 , C08F283/10 , C08G59/50 , C08G59/58 , C08J2363/00
摘要： Disclosed is a curable epoxy resin composition having excellent flexibility and toughness, comprising (a) an epoxy resin, (b) a glycol type di(meth)acrylate, (c) a nitrogen containing heterocyclic compound, and (d) a polyamine having at least two amino groups with an active hydrogen. The resin composition is very suitable for a vibration damping laminate.
摘要翻译：公开了具有优异的柔韧性和韧性的可固化环氧树脂组合物，其包含（a）环氧树脂，（b）二醇型二（甲基）丙烯酸酯，（c）含氮杂环化合物和（d）至少两个具有活性氢的氨基。该树脂组合物非常适用于减震层压板。

47. 发明授权

US4323702A Process for recovering a carboxylic acid 失效
标题翻译：回收羧酸的方法
公开(公告)号：US4323702A
公开(公告)日：1982-04-06
申请号：US207796
申请日：1980-11-17
申请人： Nariyoshi Kawabata , Shinichi Yasuda , Takeshi Yamazaki
发明人： Nariyoshi Kawabata , Shinichi Yasuda , Takeshi Yamazaki
IPC分类号： C07C51/00 , C07C51/47 , C07C67/00 , C07C227/00 , C07C227/40 , C07C227/42 , C07C51/42 , C07C53/00 , C07C59/48 , C07C65/10
CPC分类号： C07C51/47
摘要： A process for recovering carboxylic acids with a material of which the main component is a polymeric compound having a pyridine skeletal structure and a crosslinked structure, followed by desorbing the captured carboxylic acids by use of a desorbing agent.
摘要翻译：一种用主要成分为具有吡啶骨架结构和交联结构的聚合物的材料回收羧酸的方法，然后通过使用解吸剂解吸捕获的羧酸。

48. 发明授权

US3932421A Process for producing alkylpyridines 失效
标题翻译：制备烷基吡啶的方法
公开(公告)号：US3932421A
公开(公告)日：1976-01-13
申请号：US159548
申请日：1971-07-02
申请人： Yoshizo Minato , Shinichi Yasuda
发明人： Yoshizo Minato , Shinichi Yasuda
IPC分类号： B01J27/185 , C07D213/10
CPC分类号： C07D213/10 , B01J27/1853
摘要： Alkylpyridines such as 2-picoline and 4-picoline are prepared by contacting acetaldehyde and ammonia in a gaseous phase with a phosphate of two metals such as cobalt magnesium phosphate, cobalt aluminum phosphate or lead aluminum phosphate, impregnated with an aqueous solution of phosphoric acid or ammonium phosphate, as a catalyst, at a temperature of 350.degree. to 500.degree.C and a space velocity of 200 to 2,000 Hr.sup.-.sup.1. Silica-alumina and a promoter can be added to the catalyst. The impregnated catalyst has a higher catalytic activity and holds the initial high activity even after a considerable number of regeneration.
摘要翻译：通过将乙醛和氨与气相中的两种金属如磷酸钴钾，磷酸钴铝或磷酸铅或磷酸盐的磷酸盐接触，制备烷基吡啶如2-甲基吡啶和4-甲基吡啶，浸渍磷酸水溶液或磷酸铵作为催化剂，在350-500℃的温度和200-2,000Hr -1的空间速度下进行。可将二氧化硅 - 氧化铝和助催化剂加入到催化剂中。浸渍的催化剂具有更高的催化活性，并且即使在相当多的再生之后也保持初始的高活性。

49. 发明授权

US08930428B2 Random number generation circuit 有权
标题翻译：随机数生成电路
公开(公告)号：US08930428B2
公开(公告)日：2015-01-06
申请号：US13428150
申请日：2012-03-23
申请人： Shinichi Yasuda , Kazutaka Ikegami
发明人： Shinichi Yasuda , Kazutaka Ikegami
IPC分类号： G06F7/58 , H03K3/84
CPC分类号： H03K3/84 , G06F7/588
摘要： According to one embodiment, a random number generation circuit includes an oscillation circuit and a holding circuit. The oscillation circuit has an amplifier array and a high-noise circuit. Amplifiers are connected in series in the amplifier array, and the amplifier array has a terminal between neighboring amplifiers. The high-noise circuit is inserted between other neighboring amplifiers in the amplifier array, and the high-noise circuit generates noise required to generate jitter in an oscillation signal from the amplifier array. The holding circuit outputs, as a random number, the oscillation signal held according to a clock signal.
摘要翻译：根据一个实施例，随机数生成电路包括振荡电路和保持电路。振荡电路具有放大器阵列和高噪声电路。放大器在放大器阵列中串联连接，放大器阵列在相邻放大器之间具有一个端子。高噪声电路插入在放大器阵列中的其它相邻放大器之间，高噪声电路产生在放大器阵列的振荡信号中产生抖动所需的噪声。保持电路作为随机数输出根据时钟信号保持的振荡信号。

50. 发明授权

US08842475B2 Configuration memory 有权
标题翻译：配置内存
公开(公告)号：US08842475B2
公开(公告)日：2014-09-23
申请号：US13603666
申请日：2012-09-05
申请人： Kosuke Tatsumura , Masato Oda , Koichiro Zaitsu , Atsushi Kawasumi , Mari Matsumoto , Shinichi Yasuda
发明人： Kosuke Tatsumura , Masato Oda , Koichiro Zaitsu , Atsushi Kawasumi , Mari Matsumoto , Shinichi Yasuda
IPC分类号： G11C11/34
CPC分类号： G11C16/06 , G11C7/06 , G11C16/26
摘要： According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.
摘要翻译：根据一个实施例，配置存储器包括第一和第二数据线，第一存储器串，其包括串联连接在公共节点和第一数据线之间的至少第一和第二非易失性存储器晶体管，第二存储器串包括在公共节点和第二数据线之间串联连接的至少第三和第四非易失性存储器晶体管，以及包括连接到公共节点的第一数据保持节点和连接到公共节点的第二数据保持节点的触发器电路配置数据输出节点。

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