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41. 发明授权

US06975041B2 Semiconductor storage device having high soft-error immunity 失效
标题翻译：半导体存储装置具有高的软错误抗扰度
公开(公告)号：US06975041B2
公开(公告)日：2005-12-13
申请号：US10813038
申请日：2004-03-31
申请人： Yuuichi Hirano , Takashi Ipposhi
发明人： Yuuichi Hirano , Takashi Ipposhi
IPC分类号： G11C11/41 , G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/4125 , H01L27/1104 , Y10S257/903
摘要： A semiconductor storage device with high soft-error immunity is obtained. A semiconductor storage device has SRAM memory cells. NMOS transistors (Q1, Q4) are driver transistors, NMOS transistors (Q3, Q6) are access transistors, and PMOS transistors (Q2, Q5) are load transistors. An NMOS transistor (Q7) is a transistor for adding a resistance. The NMOS transistor (Q7) has its gate connected to a power supply (1). The NMOS transistor (Q7) has one of its source and drain connected to a storage node (ND1) and the other connected to the gates of the NMOS transistor (Q4) and the PMOS transistor (Q5). The resistance between the source and drain of the NMOS transistor (Q7) can be adjusted with the gate length, the gate width, the source/drain impurity concentration, etc., which is, for example, about several tens of kilohms (kΩ).
摘要翻译：获得具有高软误差抗扰度的半导体存储装置。半导体存储装置具有SRAM存储单元。 NMOS晶体管（Q 1，Q 4）是驱动晶体管，NMOS晶体管（Q 3，Q 6）是存取晶体管，PMOS晶体管（Q 2，Q 5）是负载晶体管。 NMOS晶体管（Q7）是用于增加电阻的晶体管。 NMOS晶体管（Q7）的栅极连接到电源（1）。 NMOS晶体管（Q7）的源极和漏极之一连接到存储节点（ND 1），另一个连接到NMOS晶体管（Q4）和PMOS晶体管（Q5）的栅极。可以通过栅极长度，栅极宽度，源极/漏极杂质浓度等来调整NMOS晶体管（Q 7）的源极和漏极之间的电阻，例如约几十千欧姆（kOmega ）。

42. 发明申请

US20050269637A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050269637A1
公开(公告)日：2005-12-08
申请号：US11137586
申请日：2005-05-26
申请人： Toshiaki Iwamatsu , Yuuichi Hirano , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Yuuichi Hirano , Takashi Ipposhi
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8244 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/105 , H01L27/11 , H01L27/12 , H01L29/786
CPC分类号： H01L29/78615 , H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/78609
摘要： A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
摘要翻译：在NMOS区域的MOS晶体管和PMOS区域之间分别设置的部分隔离绝缘膜具有这样的结构，其中从SOI层的主表面向上突出的部分比沟槽深度更大的厚度，即，（隔离部）延伸到SOI层的表面以下，部分绝缘膜下方的SOI层的厚度大于隔离部的厚度。

43. 发明授权

US06756692B2 Semiconductor storage device having high soft-error immunity 失效
标题翻译：半导体存储装置具有高的软错误抗扰度
公开(公告)号：US06756692B2
公开(公告)日：2004-06-29
申请号：US10201921
申请日：2002-07-25
申请人： Yuuichi Hirano , Takashi Ipposhi
发明人： Yuuichi Hirano , Takashi Ipposhi
IPC分类号： H01L2711
CPC分类号： G11C11/4125 , H01L27/1104 , Y10S257/903
摘要： A semiconductor storage device with high soft-error immunity is obtained. A semiconductor storage device has SRAM memory cells. NMOS transistors are driver transistors, NMOS transistors are access transistors, and PMOS transistors are load transistors. An NMOS transistor is a transistor for adding a resistance. The NMOS transistor has its gate connected to a power supply. The NMOS transistor has one of its source and drain connected to a storage node and the other connected to the gates of the NMOS transistor and the PMOS transistor. The resistance between the source and drain of the NMOS transistor can be adjusted with the gate length, the gate width, the source/drain impurity concentration, etc., which is, for example, about several tens of kilohms (k &OHgr;).
摘要翻译：获得具有高软误差抗扰度的半导体存储装置。半导体存储装置具有SRAM存储单元。 NMOS晶体管是驱动晶体管，NMOS晶体管是存取晶体管，PMOS晶体管是负载晶体管。 NMOS晶体管是用于增加电阻的晶体管。 NMOS晶体管的栅极连接到电源。 NMOS晶体管的源极和漏极之一连接到存储节点，另一个连接到NMOS晶体管和PMOS晶体管的栅极。 NMOS晶体管的源极和漏极之间的电阻可以通过栅极长度，栅极宽度，源极/漏极杂质浓度等进行调整，例如大约几十千欧姆（kΩ）。

44. 发明授权

US06459125B2 SOI based transistor inside an insulation layer with conductive bump on the insulation layer 失效
标题翻译：绝缘层内的SOI基晶体管，绝缘层上有导电凸块
公开(公告)号：US06459125B2
公开(公告)日：2002-10-01
申请号：US09122863
申请日：1998-07-27
申请人： Shigenobu Maeda , Tadashi Nishimura , Kazuhito Tsutsumi , Shigeto Maegawa , Yuuichi Hirano
发明人： Shigenobu Maeda , Tadashi Nishimura , Kazuhito Tsutsumi , Shigeto Maegawa , Yuuichi Hirano
IPC分类号： H01L2900
CPC分类号： H01L23/556 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/12 , H01L29/786 , H01L2224/03914 , H01L2224/0401 , H01L2224/05624 , H01L2224/11334 , H01L2224/1148 , H01L2224/1191 , H01L2224/13022 , H01L2224/131 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/0102 , H01L2924/01022 , H01L2924/01028 , H01L2924/01033 , H01L2924/0105 , H01L2924/01068 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/3025 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).
摘要翻译：提供用于CSP安装的半导体器件，其避免由于α射线引起的误差并且具有高抗应力。在半导体衬底（101）上形成掩埋氧化膜（107），在掩埋氧化膜（107）上形成具有SOI结构的MOS晶体管。 MOS晶体管包括形成在半导体层（120）中的源区和漏区（120a，120b）和栅电极（110）。通过未示出的连接机构连接到源极和漏极区域（120a，120b）中的任何一个的铝焊盘（103）和在铝焊盘（103）的顶部具有开口的氮化硅膜（104）形成在层间绝缘膜（108）上。形成从铝焊盘（103）向氮化硅膜（104）的一端延伸的钛（105）层和镍层（106）。焊料凸块（11）设置在镍层（106）上。

45. 发明申请

US20080067593A1 Semiconductor device 审中-公开
公开(公告)号：US20080067593A1
公开(公告)日：2008-03-20
申请号：US11979120
申请日：2007-10-31
申请人： Toshiaki Iwamatsu , Yuuichi Hirano , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Yuuichi Hirano , Takashi Ipposhi
IPC分类号： H01L27/01
CPC分类号： H01L29/78615 , H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/78609
摘要： A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

46. 发明授权

US07332776B2 Semiconductor device 有权
公开(公告)号：US07332776B2
公开(公告)日：2008-02-19
申请号：US11826569
申请日：2007-07-17
申请人： Toshiaki Iwamatsu , Yuuichi Hirano , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Yuuichi Hirano , Takashi Ipposhi
IPC分类号： H01L27/01
CPC分类号： H01L29/78615 , H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/78609
摘要： A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

47. 发明申请

US20080001226A1 Semiconductor memory device and method of manufacturing the same 失效
公开(公告)号：US20080001226A1
公开(公告)日：2008-01-03
申请号：US11889677
申请日：2007-08-15
申请人： Yuuichi Hirano , Takashi Ipposhi , Shigeto Maegawa , Koji Nii
发明人： Yuuichi Hirano , Takashi Ipposhi , Shigeto Maegawa , Koji Nii
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/11 , H01L27/1108 , H01L27/1203 , Y10S257/903 , Y10S257/904
摘要： A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

48. 发明申请

US20070257330A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070257330A1
公开(公告)日：2007-11-08
申请号：US11826569
申请日：2007-07-17
申请人： Toshiaki Iwamatsu , Yuuichi Hirano , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Yuuichi Hirano , Takashi Ipposhi
IPC分类号： H01L29/00
CPC分类号： H01L29/78615 , H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/78609
摘要： A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
摘要翻译：在NMOS区域的MOS晶体管和PMOS区域之间分别设置的部分隔离绝缘膜具有这样的结构，其中从SOI层的主表面向上突出的部分比沟槽深度更大的厚度，即，（隔离部）延伸到SOI层的表面以下，部分绝缘膜下方的SOI层的厚度大于隔离部的厚度。

49. 发明授权

US07271454B2 Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07271454B2
公开(公告)日：2007-09-18
申请号：US10927638
申请日：2004-08-27
申请人： Yuuichi Hirano , Takashi Ipposhi , Shigeto Maegawa , Koji Nii
发明人： Yuuichi Hirano , Takashi Ipposhi , Shigeto Maegawa , Koji Nii
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/11 , H01L27/1108 , H01L27/1203 , Y10S257/903 , Y10S257/904
摘要： A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.
摘要翻译：连接到字线的触点形成在SRAM单元的存取晶体管的栅电极上。接触通过元件隔离绝缘膜以达到SOI层。驱动晶体管的体区和存取晶体管的体区通过位于元件隔离绝缘膜下方的SOI层彼此电连接。因此，存取晶体管是具有通过触点与主体区域连接的栅电极的DTMOS结构，该触点又电连接到驱动晶体管的体区。因此，可以在抑制用于形成SRAM单元的区域的增加的同时稳定操作。

50. 发明申请

US20060086980A1 Semiconductor device, SRAM and manufacturing method of semiconductor device 失效
公开(公告)号：US20060086980A1
公开(公告)日：2006-04-27
申请号：US11250382
申请日：2005-10-17
申请人： Yuuichi Hirano , Takashi Ipposhi
发明人： Yuuichi Hirano , Takashi Ipposhi
IPC分类号： H01L27/12
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： A semiconductor device according to the present invention is provided with an SOI substrate, an active region, a first insulating film (complete separation insulating film), a second insulating film (partial separation insulating film), and a contact portion. Here, the active region is formed within the surface of the SOI layer. In addition, the first insulating film is formed on one side of the active region from the surface of SOI layer to the buried insulating film. In addition, the second insulating film is formed on the other side of the active region from the surface of SOI layer to a predetermined depth that does not reach the buried insulating film. In addition, the contact portion is provided toward the side where the first insulating film exists, off the center of the active region in a plan view.

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