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41. 发明授权

US6167474A Apparatus and method for distributed arbitration of shared resources 失效
标题翻译：共享资源的分布式仲裁的装置和方法
公开(公告)号：US6167474A
公开(公告)日：2000-12-26
申请号：US015587
申请日：1998-01-29
申请人： Sherman Lee
发明人： Sherman Lee
IPC分类号： G06F12/06 , G06F13/376 , G06F13/40 , G06F13/00
CPC分类号： G06F13/409 , G06F12/0676 , G06F13/376
摘要： A novel distributed arbitration apparatus in accordance with this invention includes a plurality of electrical devices, such as Industry Standard Architecture (ISA) hub cards, that independently determine availability of a shared resource, such as a bus that interconnects the devices, by use of an arbiter. When a circuit in an electrical device needs to use the bus, the circuit drives a request signal active to an arbiter, for example, in the form of a programmable logic device, such as a Programmable Array Logic (PAL.TM.) device included in the electrical device. The arbiter in turn transmits the request signal to all other arbiters. Therefore, each arbiter receives and monitors request signals from all circuits. If only one request signal is active at a given time, all arbiters receive the active request signal and each arbiter drives an acknowledge signal active to the respective local circuit. The circuit that requested the shared resource then uses the resource. If more than one request signal is active simultaneously, each arbiter determines the occurrence of a collision, and drives a collision signal active to the respective local circuit that then implements a backoff algorithm.
摘要翻译：根据本发明的新颖的分布式仲裁装置包括多个电气装置，例如工业标准架构（ISA）集线器卡，其独立地确定共享资源的可用性，例如通过使用仲裁者。当电气设备中的电路需要使用总线时，电路驱动对仲裁器有效的请求信号，例如以可编程逻辑器件的形式，例如包括在该器件中的可编程阵列逻辑（PAL TM）器件电气设备。仲裁者又向所有其他仲裁者发送请求信号。因此，每个仲裁器接收并监视来自所有电路的请求信号。如果在给定时间只有一个请求信号被激活，则所有仲裁器都接收到有效请求信号，并且每个仲裁器驱动对相应本地电路有效的确认信号。然后请求共享资源的电路使用该资源。如果多个请求信号同时被激活，则每个仲裁器确定碰撞的发生，并且驱动对相应的本地电路有效的冲突信号，然后实现退避算法。

42. 发明授权

US5870554A Server selection method where a client selects a server according to address, operating system and found frame for remote booting 失效
标题翻译：服务器选择方法，其中客户端根据地址，操作系统和找到的框架来选择服务器进行远程启动
公开(公告)号：US5870554A
公开(公告)日：1999-02-09
申请号：US626683
申请日：1996-04-01
申请人： Leonid Grossman , Sherman Lee
发明人： Leonid Grossman , Sherman Lee
IPC分类号： G06F9/445 , H04L29/06 , H04L29/08 , G06F9/40
CPC分类号： G06F9/4416 , H04L67/1008
摘要： A method for choosing a particular server on a network and performing a remote boot by a client, the network including a plurality of servers operating in accordance with a plurality of network operating systems, includes identifying each of the plurality of servers by address and by type of operating system, and selecting one of the identified servers by address and type for booting on the network. Identifying further includes sending a FIND frame from the client to the network, and receiving a FOUND frame from each of the plurality of servers. A remote program load protocol followed by the server according to the FOUND frame is determined.Additionally, choosing a particular server on a network and performing a remote boot by a client includes identifying each of a plurality of servers according to characteristics of a FOUND frame including a frequency characteristic, selecting one of the identified servers, and performing a remote program load by a boot ROM on a client through the selected one of the identified plurality of servers. Identifying further includes determining whether a destination address of the FOUND frame is repeated in a same order in a data portion of the FOUND frame, wherein when the destination address is repeated in a same order, a frequency characteristic of the FOUND frame is determined.
摘要翻译：一种用于在网络上选择特定服务器并由客户机执行远程启动的方法，所述网络包括根据多个网络操作系统操作的多个服务器，所述方法包括通过地址和类型来识别所述多个服务器中的每一个的操作系统，并通过地址和类型在网络上引导来选择一个已识别的服务器。识别还包括将FIND帧从客户端发送到网络，以及从多个服务器中的每一个接收FOUND帧。确定根据FOUND帧的服务器后面的远程程序加载协议。另外，选择网络上的特定服务器并且由客户端执行远程引导包括根据包括频率特性的FOUND帧的特性来识别多个服务器中的每一个，选择所识别的服务器之一以及执行远程程序负载通过所选择的一个所识别的多个服务器中的客户机上的引导ROM。识别还包括确定在FOUND帧的数据部分中是否以相同的顺序重复FOUND帧的目的地地址，其中当以相同的顺序重复目的地地址时，确定FOUND帧的频率特性。

43. 发明授权

US5860024A Microprocessor with automatic name generation including performance indication 失效
标题翻译：具有自动名称生成的微处理器，包括性能指示
公开(公告)号：US5860024A
公开(公告)日：1999-01-12
申请号：US631941
申请日：1996-04-15
申请人： David G. Kyle , Sherman Lee
发明人： David G. Kyle , Sherman Lee
IPC分类号： G06F11/00 , G06F11/24 , G06F11/27 , G01K23/00
CPC分类号： G06F11/24 , G06F11/006
摘要： A microprocessor with automatic and dynamic partname determination including performance number. The microprocessor includes circuitry that measures a core clock frequency for the microprocessor and circuitry that determines a performance indication for the microprocessor in response to the measured core clock frequency.
摘要翻译：具有自动和动态部分名称确定的微处理器，包括性能数字。微处理器包括测量微处理器和电路的核心时钟频率的电路，该电路根据所测量的核心时钟频率确定微处理器的性能指示。

44. 发明授权

US5812425A Method for changing operation of circuitry in a CPU based on a statistic of performance of the CPU 失效
标题翻译：基于CPU的性能统计来改变CPU中电路的运行的方法
公开(公告)号：US5812425A
公开(公告)日：1998-09-22
申请号：US710294
申请日：1996-09-16
申请人： Sherman Lee , David G. Kyle
发明人： Sherman Lee , David G. Kyle
IPC分类号： G06F9/38 , G06F11/34 , G06F12/08 , G06F15/78 , G06F11/26 , G06F11/00
CPC分类号： G06F9/3885 , G06F11/3452 , G06F15/7867 , G06F9/30036 , G06F9/3897 , G06F12/0802 , G06F2201/86 , G06F2201/885 , G06F2212/601
摘要： A computer process transforms a "general purpose" central processing unit (hereinafter "CPU") into one of a number of possible "special purpose" CPUs by changing operation of circuitry in the CPU. Changing operation of CPU circuitry as described herein "fine tunes" behavior of the CPU, e.g. provides resources and environment most suitable for execution of a specific application program, or even a portion of an application program. The computer process performs the steps of: checking whether the CPU has a tunable unit, waiting for a triggering event indicating a need for fine tuning, reading one or more statistics on the performance of the CPU, comparing the read statistics with corresponding predetermined statistics, determining a multi-valued parameter signal depending on the comparison, driving the determined parameter signal to the tunable unit and changing operation of circuitry in the tunable unit depending on the received parameter signal, thereby to fine tune operation of the tunable unit and the CPU.
摘要翻译：计算机处理通过改变CPU中的电路的操作将“通用”中央处理单元（以下称为“CPU”）转换成多个可能的“专用”CPU之一。如本文所述改变CPU电路的操作“CPU的微调”行为，例如，提供最适合于执行特定应用程序或甚至应用程序的一部分的资源和环境。计算机处理执行以下步骤：检查CPU是否具有可调谐单元，等待指示需要微调的触发事件，读取关于CPU的性能的一个或多个统计信息，将读取的统计与相应的预定统计比较，根据比较确定多值参数信号，将确定的参数信号驱动到可调单元，并根据接收到的参数信号改变可调单元中的电路的运行，从而微调可调单元和CPU的操作。

45. 发明授权

US5799203A System for receiving peripheral device capability information and selectively disabling corresponding processing unit function when the device failing to support such function 失效
标题翻译：用于接收外围设备能力信息的系统，并且当设备不能支持该功能时选择性地禁用对应的处理单元功能
公开(公告)号：US5799203A
公开(公告)日：1998-08-25
申请号：US649537
申请日：1996-05-17
申请人： Sherman Lee , James R. MacDonald , Michael T. Wisor
发明人： Sherman Lee , James R. MacDonald , Michael T. Wisor
IPC分类号： G06F11/22 , G06F15/177 , G06F13/00
CPC分类号： G06F9/4411 , G06F11/2289 , G06F15/177
摘要： A system and method for providing information regarding system support capabilities to a processor. A computer system includes a processing unit, a main memory and a first plurality of peripherals coupled to a first bus. A bus bridge couples the first bus to a second bus and a second plurality of support peripherals are coupled to the second bus. The processing unit is capable of providing requests for system support information to the bus bridge and the first and second plurality support peripherals. The peripherals are configured to provide responses to the request. The processing unit stores the responses and uses the information received to enable and disable its functional units or the peripheral's functional units accordingly. In one embodiment, the requests and information are provided along a dedicated serial interface. In another, the requests and information are provided as specialized bus cycles along the CPU bus.
摘要翻译：一种用于向处理器提供关于系统支持能力的信息的系统和方法。计算机系统包括处理单元，主存储器和耦合到第一总线的第一多个外围设备。总线桥将第一总线耦合到第二总线，并且第二多个支持外围设备耦合到第二总线。处理单元能够向总线桥以及第一和第二多个支持外围设备提供系统支持信息的请求。外设被配置为提供对请求的响应。处理单元存储响应并使用所接收的信息来相应地启用和禁用其功能单元或外围设备的功能单元。在一个实施例中，沿着专用串行接口提供请求和信息。另一方面，请求和信息作为沿CPU总线的专用总线周期提供。

46. 发明授权

US5790041A Apparatus and method to display network connection status on a jack panel 失效
标题翻译：在插孔面板上显示网络连接状态的装置和方法
公开(公告)号：US5790041A
公开(公告)日：1998-08-04
申请号：US388646
申请日：1995-02-14
申请人： Sherman Lee
发明人： Sherman Lee
IPC分类号： H01R13/518 , H01R13/713 , H05K1/18 , G08B5/22 , H01R3/00
CPC分类号： H01R13/713 , H01R13/518 , H01R24/64 , H05K1/18 , Y10S439/91
摘要： A jack has a side opening that allows light from a light emitter that is mounted adjacent to the side opening to enter the jack's cavity and emerge from the jack's front opening that is used for insertion of a plug. In one embodiment, when a plug is inserted into the jack, a transparent portion of the plug allows the light to emerge from a posterior end of the plug to provide a visible indication of the state of the connection between the jack and the plug. Emergence of light from the jack's front opening results in saving space on a jack panel because panel space conventionally used for a LED is no longer needed. The side opening is located adjacent to the jack's bottom surface that is adjacent to a printed circuit board (PCB) on which the jack is mounted. In one embodiment, the light emitter is mounted on the PCB near the side opening between the jack's bottom surface and the PCB's top surface. Using the PCB space underneath the jack's bottom surface frees up PCB space that is conventionally used for supporting LEDs.
摘要翻译：插座具有侧开口，其允许来自安装在侧开口附近的发光器的光进入插座的腔并从插座的插孔的前开口露出。在一个实施例中，当插头插入插座时，插头的透明部分允许光从插头的后端露出以提供插座和插头之间的连接状态的可视指示。千斤顶的前开口的光线的出现导致节省了千斤顶面板上的空间，因为不再需要常规用于LED的面板空间。侧面开口位于与插座安装在其上的印刷电路板（PCB）相邻的插孔底面附近。在一个实施例中，光发射器安装在印刷电路板附近，位于插座的底部表面和PCB的顶部表面之间的侧面开口处。使用插座底面下方的PCB空间可以释放通常用于支持LED的PCB空间。

47. 发明授权

US5754777A Apparatus and method for distributed arbitration of shared resources 失效
公开(公告)号：US5754777A
公开(公告)日：1998-05-19
申请号：US434358
申请日：1995-05-05
申请人： Sherman Lee
发明人： Sherman Lee
IPC分类号： G06F12/06 , G06F13/376 , G06F13/40 , G06F13/14
CPC分类号： G06F13/409 , G06F12/0676 , G06F13/376
摘要： A novel distributed arbitration apparatus in accordance with this invention includes a plurality of electrical devices, such as Industry Standard Architecture (ISA) hub cards, that independently determine availability of a shared resource, such as a bus that interconnects the devices, by use of an arbiter. When a circuit in an electrical device needs to use the bus, the circuit drives a request signal active to an arbiter, for example, in the form of a programmable logic device, such as a Programmable Array Logic (PAL.TM.) device included in the electrical device. The arbiter in turn transmits the request signal to all other arbiters. Therefore, each arbiter receives and monitors request signals from all circuits. If only one request signal is active at a given time, all arbiters receive the active request signal and each arbiter drives an acknowledge signal active to the respective local circuit. The circuit that requested the shared resource then uses the resource. If more than one request signal is active simultaneously, each arbiter determines the occurrence of a collision, and drives a collision signal active to the respective local circuit that then implements a backoff algorithm.

48. 发明授权

US4870622A DRAM controller cache 失效
标题翻译： DRAM控制器缓存
公开(公告)号：US4870622A
公开(公告)日：1989-09-26
申请号：US211511
申请日：1988-06-24
申请人： Percy R. Aria , Sherman Lee
发明人： Percy R. Aria , Sherman Lee
IPC分类号： G11C11/401 , G06F12/02 , G11C7/10 , G11C11/4096
CPC分类号： G11C7/1018 , G06F12/0215 , G11C11/4096
摘要： A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same row but in different columns. First data is accessed at a predetermined column and row location. The predetermined row location of the first data is then recorded. The location of second data is then recorded. Then the locations of the first and second data are compared. A row compare signal is generated if the row value of both first and second data are identical. Only the column address is varied in response to the row compare signal.

49. 发明授权

US07167727B2 Wireless data communications using FIFO for synchronization memory 失效
标题翻译：无线数据通信使用FIFO进行同步存储
公开(公告)号：US07167727B2
公开(公告)日：2007-01-23
申请号：US10674693
申请日：2003-09-30
申请人： Sherman Lee , Vivian Y. Chou , John H. Lin
发明人： Sherman Lee , Vivian Y. Chou , John H. Lin
IPC分类号： H04B1/38
CPC分类号： G06F9/328 , G06F8/66 , G06F9/268 , H04B1/7156 , H04B2001/71566 , H04J3/062 , H04L25/05 , H04W84/18 , H04W88/02
摘要： A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.
摘要翻译：无线（Radio）接收机接收携带与第一时钟同步的数据的RF信号。无线接收机解调RF信号以提取数据信号和第一时钟信号。无线接收机使用第一时钟信号作为写入信号，以先进先出的存储器件（FIFO）来写入数据信号。存储在FIFO中的数据信号可以用与第二时钟同步的读取信号读出。在一个示例中，与无线接收器相关联的主机以与主机接收机的系统时钟同步的读取信号读出存储在FIFO中的数据信号。在另一示例中，无线接收器包括数据处理电路（例如，包括前向纠错，去白化和循环冗余校验电路），其读出存储在FIFO中的数据信号，其中读取信号与无线系统时钟同步接收器。公开了一种微处理器系统架构，其允许选择性地执行编程的ROM微代码，或者替代地，如果已经对最初编程到系统中的ROM微代码进行了校正或更新，则可以选择性地执行RAM微代码。修补或更新的RAM微代码仅在ROM微代码的改变程度上被使用或执行，否则ROM微代码以其正常方式执行。当接收到补丁时，它将与指令或其他适当的信号一起加载到系统RAM中，以指导来自RAM的修补或更新的微代码的执行，而不是现有的ROM微代码。呈现各种方法用于根据是否对其进行了改变来选择适当的微代码的执行。

50. 发明授权

US5923852A Method and system for fast data transmissions in a processing system utilizing interrupts 失效
标题翻译：在利用中断的处理系统中快速数据传输的方法和系统
公开(公告)号：US5923852A
公开(公告)日：1999-07-13
申请号：US708308
申请日：1996-09-04
申请人： Sherman Lee , Ramkrishna Vepa , Robert Alan Williams
发明人： Sherman Lee , Ramkrishna Vepa , Robert Alan Williams
IPC分类号： G06F13/00 , H04L12/56 , H04L13/08 , G06F17/00
CPC分类号： H04L49/901 , H04L49/90
摘要： A system and method for facilitates a fast transmission of packet information into the buffers without unnecessary delays, thereby increasing overall system performance. The method and system comprises sending a packet of information located in a local buffer to a media, generating an interrupt signal indicating a completed transfer of the packet to the media and availability of the local buffer for receiving a next packet, and sending the next packet of information from a queue to the local buffer in response to the interrupt signal, wherein the generation of the interrupt signal after each data packet is transmitted to the media does not affect the overall operation of the processing system.
摘要翻译：一种用于促进将分组信息快速传输到缓冲器而不需要不必要的延迟的系统和方法，从而提高整个系统性能。所述方法和系统包括将位于本地缓冲器中的信息分组发送到媒体，产生指示分组到媒体的完整传送的中断信号以及用于接收下一分组的本地缓冲器的可用性，以及发送下一分组响应于中断信号从队列到本地缓冲器的信息，其中在每个数据分组被发送到媒体之后生成中断信号不影响处理系统的整体操作。

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