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41. 发明申请

US20090166629A1 REDUCING GATE CD BIAS IN CMOS PROCESSING 有权
标题翻译：降低CMOS加工中的门偏移
公开(公告)号：US20090166629A1
公开(公告)日：2009-07-02
申请号：US12241798
申请日：2008-09-30
申请人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
发明人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/82385 , H01L21/823842
摘要： A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.
摘要翻译：公开了一种形成具有NMOS晶体管和PMOS晶体管的集成电路的方法。该方法包括在半导体主体上和/或半导体本体中的NMOS区域和PMOS区域中执行预栅极处理，以及在NMOS和PMOS区域中的半导体本体上沉积多晶硅层。该方法还包括在NMOS区域和PMOS区域之一中的多晶硅层中执行第一种类型的注入，并且在NMOS和PMOS区域中的多晶硅层中进行非晶化注入，从而将多晶硅层转变为非晶硅层。该方法还包括图案化非晶硅层以形成栅电极，其中栅极位于NMOS和PMOS区两者中。

42. 发明申请

US20080268631A1 Method of Forming a Silicided Gate Utilizing a CMP Stack 有权
标题翻译：使用CMP堆叠形成硅化浇口的方法
公开(公告)号：US20080268631A1
公开(公告)日：2008-10-30
申请号：US11741064
申请日：2007-04-27
申请人： Frank Scott Johnson , Freidoon Mehrad
发明人： Frank Scott Johnson , Freidoon Mehrad
IPC分类号： H01L21/8238 , H01L21/311
CPC分类号： H01L21/823835 , H01L21/28097 , H01L29/4975 , H01L29/66545
摘要： A method for fabricating a semiconductor device includes forming a silicided gate utilizing a CMP stack. The CMP stack includes a first liner formed over the underlying semiconductor device and a first dielectric layer formed over the first liner layer. The first dielectric layer is formed to approximately the height of the gate. A second liner layer is formed over the first dielectric layer. Since the first dielectric layer is formed to approximately the height of the gate, the second liner over the moat regions is at approximately the height of the first liner over the gate. A CMP process is performed to expose the first liner over the top of the gate. Since the first dielectric layer is formed to the height of the gate, a portion of the second liner remains over the moat regions after the CMP process. Afterwards, the gate is exposed and a silicidation is performed to create a silicided gate.
摘要翻译：一种用于制造半导体器件的方法包括利用CMP叠层形成硅化栅。 CMP堆叠包括形成在下面的半导体器件上的第一衬垫和形成在第一衬里层上的第一介电层。第一电介质层形成为大约高度的栅极。在第一介电层上形成第二衬里层。由于第一电介质层形成为大致高度的栅极，护套区域上的第二衬垫大约在栅极上的第一衬垫的高度处。执行CMP处理以在栅极的顶部上露出第一衬垫。由于第一电介质层形成到栅极的高度，所以在CMP工艺之后，第二衬里的一部分保留在护环区域之上。之后，露出栅极，进行硅化处理以形成硅化栅极。

43. 发明申请

US20050059228A1 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance 有权
公开(公告)号：US20050059228A1
公开(公告)日：2005-03-17
申请号：US10662850
申请日：2003-09-15
申请人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
发明人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L29/08 , H01L29/76 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , Y10S438/902
摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

44. 发明授权

US06765257B1 Implanted vertical source-line under straight stack for flash eprom 失效
标题翻译：在垂直堆栈下注入垂直源线用于闪光eprom
公开(公告)号：US06765257B1
公开(公告)日：2004-07-20
申请号：US09120712
申请日：1998-07-22
申请人： Freidoon Mehrad , Kyle A. Picone
发明人： Freidoon Mehrad , Kyle A. Picone
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L27/115
摘要： In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical source lines.
摘要翻译：在FLASH EPROM单元中，水平和垂直源极线之间的源极扩散连续性由垂直源极线下的堆叠下的砷注入提供。

45. 发明授权

US06524930B1 Method for forming a bottom corner rounded STI 有权
标题翻译：形成底角圆角STI的方法
公开(公告)号：US06524930B1
公开(公告)日：2003-02-25
申请号：US10131958
申请日：2002-04-25
申请人： Christoph A. Wasshuber , Zhihao Chen , Freidoon Mehrad
发明人： Christoph A. Wasshuber , Zhihao Chen , Freidoon Mehrad
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： Methods are disclosed for the formation of isolation structures and trenches in semiconductor devices, in which lower corners of an isolation trench are rounded after trench formation using an oxidation process which oxidizes substrate material from the trench sidewalls and bottom faster than from the lower corners of the trench. The oxide formed during the rounding process is then removed prior to performing other etch processes, to expose substrate material having rounded lower corners. Thereafter, a liner is formed and the trench is filled with dielectric material to complete the isolation structure.
摘要翻译：公开了用于在半导体器件中形成隔离结构和沟槽的方法，其中隔离沟槽的下角在沟槽形成之后被圆化，使用氧化工艺，其从衬底材料从沟槽侧壁氧化衬底，并且底部比从沟。然后在进行其它蚀刻工艺之前去除在舍入过程中形成的氧化物，以露出具有圆形下角的衬底材料。此后，形成衬垫，并且用电介质材料填充沟槽以完成隔离结构。

46. 发明授权

US06451642B1 Method to implant NMOS polycrystalline silicon in embedded FLASH memory applications 有权
标题翻译：在嵌入式FLASH存储器应用中注入NMOS多晶硅的方法
公开(公告)号：US06451642B1
公开(公告)日：2002-09-17
申请号：US09599377
申请日：2000-06-22
申请人： Freidoon Mehrad , Jie Xia , Thomas M. Ambrose
发明人： Freidoon Mehrad , Jie Xia , Thomas M. Ambrose
IPC分类号： H01L218238
CPC分类号： H01L27/11526 , H01L21/31138 , H01L21/32137 , H01L27/105 , H01L27/11546
摘要： A method to implant NMOS polycrystalline silicon in embedded FLASH memory applications is described. In the method the polycrystalline silicon region (130) that will used to form the gate electrode of the NMOS transistor is doped simultaneously along with the source line in the FLASH memory array.
摘要翻译：描述了在嵌入式FLASH存储器应用中注入NMOS多晶硅的方法。在该方法中，将用于形成NMOS晶体管的栅极的多晶硅区域（130）与闪存存储器阵列中的源极线同时掺杂。

47. 发明授权

US06429093B1 Sidewall process for forming a low resistance source line 有权
标题翻译：用于形成低电阻源线的侧壁工艺
公开(公告)号：US06429093B1
公开(公告)日：2002-08-06
申请号：US09627258
申请日：2000-07-28
申请人： Jie Xia , Freidoon Mehrad , Mercer L. Brugler
发明人： Jie Xia , Freidoon Mehrad , Mercer L. Brugler
IPC分类号： H01L2176
CPC分类号： H01L27/11521 , H01L21/28518 , H01L21/3185 , H01L21/823481 , H01L27/115 , H01L29/66545
摘要： A method of forming a semiconductor component having a conductive line (24) and a silicide region (140) that crosses a trench (72). The method involves forming nitride sidewalls (127) to protect the stack during the silicidation process.
摘要翻译：一种形成具有导电线（24）和穿过沟槽（72）的硅化物区域（140）的半导体部件的方法。该方法包括在硅化过程中形成氮化物侧壁（127）以保护堆叠。

48. 发明授权

US06268248B1 Method of fabricating a source line in flash memory having STI structures 有权
标题翻译：在具有STI结构的闪速存储器中制造源极线的方法
公开(公告)号：US06268248B1
公开(公告)日：2001-07-31
申请号：US09215478
申请日：1998-12-18
申请人： Freidoon Mehrad
发明人： Freidoon Mehrad
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of forming a semiconductor component having a conductive line (24) that crosses a trench (72) may include forming the trench (72) in a semiconductor substrate (52). A dopant may be implanted at a first energy level into the semiconductor substrate (52) to form a first conductive region (92). The dopant may be implanted at a second energy level into the semiconductor substrate (52) to form a second conductive region (94). The first energy level may be greater than the second energy level. The first conductive region (92) and the second conductive region (94) may form the conductive line (24).
摘要翻译：形成具有穿过沟槽（72）的导线（24）的半导体部件的方法可以包括在半导体衬底（52）中形成沟槽（72）。掺杂剂可以以第一能级注入到半导体衬底（52）中以形成第一导电区域（92）。掺杂剂可以以第二能级注入到半导体衬底（52）中以形成第二导电区域（94）。第一能级可能大于第二能级。第一导电区域（92）和第二导电区域（94）可以形成导线（24）。

49. 发明授权

US07670952B2 Method of manufacturing metal silicide contacts 有权
标题翻译：制造金属硅化物接触的方法
公开(公告)号：US07670952B2
公开(公告)日：2010-03-02
申请号：US11690643
申请日：2007-03-23
申请人： Yaw S. Obeng , Juanita DeLoach , Freidoon Mehrad
发明人： Yaw S. Obeng , Juanita DeLoach , Freidoon Mehrad
IPC分类号： H01L21/311
CPC分类号： H01L21/823835 , H01L21/02068 , H01L21/28518 , H01L21/823871
摘要： A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底表面上形成金属硅化物栅电极。该方法还包括将金属硅化物栅电极和衬底表面暴露于清洁过程。清洁过程包括使用含无水氟化物的进料气体的干等离子体蚀刻和被配置为使金属硅化物栅电极基本上保持不变的热升华。该方法还包括在衬底表面的源极和漏极区域上沉积金属层并退火衬底表面的金属层和源极和漏极区域以形成金属硅化物源极和漏极接触。

50. 发明申请

US20090191675A1 Method for Forming CMOS Transistors Having FUSI Gate Electrodes and Targeted Work Functions 有权
标题翻译：用于形成具有FUSI栅极电极和目标功能的CMOS晶体管的方法
公开(公告)号：US20090191675A1
公开(公告)日：2009-07-30
申请号：US12022488
申请日：2008-01-30
申请人： Freidoon Mehrad , Frank S. Johnson
发明人： Freidoon Mehrad , Frank S. Johnson
IPC分类号： H01L21/8238
CPC分类号： H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A method for making CMOS transistors that includes forming a NMOS transistor and a PMOS transistor having an undoped polysilicon gate electrode and a hardmask. The method also includes forming a layer of insulating material and then removing the hardmasks and a portion of the layer of insulating material. A layer of silicidation metal is formed and a first silicide anneal changes the undoped polysilicon gate electrodes into partially silicided gate electrodes. Dopants of a first type and a second type are implanted into the partially silicided gate electrode of the PMOS and NMOS transistors and a second silicide anneal is performed to change the doped partially silicided gate electrodes into fully silicided gate electrodes.
摘要翻译：一种制造CMOS晶体管的方法，包括形成NMOS晶体管和具有未掺杂多晶硅栅电极和硬掩模的PMOS晶体管。该方法还包括形成绝缘材料层，然后去除硬掩模和绝缘材料层的一部分。形成硅化金属层，并且第一硅化物退火将未掺杂的多晶硅栅电极改变成部分硅化栅电极。将第一类型和第二类型的掺杂剂注入到PMOS和NMOS晶体管的部分硅化物栅电极中，并且执行第二硅化物退火以将掺杂的部分硅化栅电极改变为完全硅化的栅电极。

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