专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US06560687B1 Method of implementing a translation lookaside buffer with support for a real space control 有权
标题翻译：实现支持实际空间控制的翻译后备缓冲器的方法
公开(公告)号：US06560687B1
公开(公告)日：2003-05-06
申请号：US09677345
申请日：2000-10-02
申请人： Aaron Tsai , Chung-Lung Kevin Shum , Dean G. Bair , Rebecca S. Wisniewski , Charles F. Webb
发明人： Aaron Tsai , Chung-Lung Kevin Shum , Dean G. Bair , Rebecca S. Wisniewski , Charles F. Webb
IPC分类号： G06F1200
CPC分类号： G06F12/1027
摘要： To support a new processor control bit, the Real Space Control (RSC) bit, in a processor system with an existing translation lookaside buffer, an existing control bit, the Private Space bit, in the translation lookaside buffer is redefined as an Ignore Common segment bit to create new non-overlapping translation lookaside buffer entries.
摘要翻译：为了支持新的处理器控制位，在具有现有转换后备缓冲器的处理器系统中的实际空间控制（RSC）位将翻译后置缓冲器中的现有控制位，专用空间位重新定义为忽略公共段位创建新的非重叠翻译后备缓冲区条目。

42. 发明授权

US06233655B1 Method for Quad-word Storing into 2-way interleaved L1 cache 失效
标题翻译：用于四字存储到双向交错L1缓存的方法
公开(公告)号：US06233655B1
公开(公告)日：2001-05-15
申请号：US09070146
申请日：1998-04-30
申请人： Chung-Lung Kevin Shum , Wen He Li , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Wen He Li , Charles Franklin Webb
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F12/0851 , G06F12/0886
摘要： A computer processor has an I-unit (instruction unit) and instruction decoder, an E-unit (execution unit), a Buffer Control Element (BCE) containing a unified two-way interleaved L1 cache and providing write control to said two-way interleaved L1 cache. The processor has Double Word wide execution dataflow. An instruction decoder receiving instruction data from a unified cache before decoding causes, for stores, I-unit logic to initiate a request ahead of execution to tell the buffer control element that stores will be made from the E-unit, and E-unit logic sends a store request to initiate a store after decoding corresponding instruction data which indicates what address in the cache the DoubleWord data is to be stored to. In the process, E-unit logic calculates, from source and destination address information address ranges information in an instruction, whether a corresponding multi-Double Word store with same byte data will result from the data patterns, and, when a multi-Double Word store could result, it enables the E-unit to request the writing of an incoming Double Word on the computer's data bus for both Double Word L1 cache interleaves using the same address for both to effectively write two consecutively addressed DoubleWords for the same cycle to achieve a Quad Word store in a cycle.
摘要翻译：计算机处理器具有I单元（指令单元）和指令解码器，E单元（执行单元），包含统一双向交错L1高速缓存的缓冲器控制元件（BCE），并向所述双向交错L1缓存。处理器具有双字宽执行数据流。在解码之前从统一高速缓存器接收指令数据的指令解码器使存储I单元逻辑在执行之前启动请求以告知缓冲器控制元件将从E单元进行存储，并且E单元逻辑在对相应的指令数据进行解码之后发送存储请求，以指示高速缓存中要存储的DoubleWord数据的哪个地址。在该过程中，E单元逻辑根据指令中的源地址信息和目的地址信息地址范围信息，计算出数据模式是否产生具有相同字节数据的对应多双字存储，以及当多单字存储可能导致，它使E单元能够使用相同的地址在计算机的数据总线上请求输入双字的双字L1高速缓存交错，以便在相同周期内有效地写入两个连续寻址的DoubleWords来实现一个四周商店在一个循环。

43. 发明授权

US09164761B2 Obtaining data in a pipelined processor 有权
标题翻译：在流水线处理器中获取数据
公开(公告)号：US09164761B2
公开(公告)日：2015-10-20
申请号：US12033351
申请日：2008-02-19
申请人： Aaron Tsai , Bruce C. Giamei , Chung-Lung Kevin Shum , Scott B. Swaney
发明人： Aaron Tsai , Bruce C. Giamei , Chung-Lung Kevin Shum , Scott B. Swaney
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/3879
摘要： A pipelined processor including one or more units having storage locations not directly accessible by software instructions. The processor includes a load-store unit (LSU) in direct communication with the one or more units for accessing the storage locations in response to special instructions. The processor also includes a requesting unit for receiving a special instruction from a requestor and a mechanism for performing a method. The method includes broadcasting storage location information from the special instruction to one or more of the units to determine a corresponding unit having the storage location specified by the special instruction. Execution of the special instruction is initiated at the corresponding unit. If the unit executing the special instruction is not the LSU, the data is sent to the LSU. The data is received from the LSU as a result of the execution of the special instruction. The data is provided to the requester.
摘要翻译：流水线处理器包括一个或多个单元，其具有不能由软件指令直接访问的存储位置。处理器包括与一个或多个单元直接通信的加载存储单元（LSU），用于响应于特殊指令访问存储位置。处理器还包括用于从请求者接收特殊指令的请求单元和用于执行方法的机制。该方法包括将特定指令中的存储位置信息广播到一个或多个单元，以确定具有由特殊指令指定的存储位置的对应单元。特殊指令的执行在相应的单位启动。如果执行特殊指令的单元不是LSU，则将数据发送到LSU。作为执行特殊指令的结果，从LSU接收数据。数据被提供给请求者。

44. 发明授权

US08627047B2 Store data forwarding with no memory model restrictions 有权
标题翻译：存储数据转发，无内存模式限制
公开(公告)号：US08627047B2
公开(公告)日：2014-01-07
申请号：US12031898
申请日：2008-02-15
申请人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
发明人： Aaron Tsai , Barry W. Krumm , James R. Mitchell , Bradley Nelson , Brian D. Barrick , Chung-Lung Kevin Shum , Michael H. Wood
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0855 , G06F9/3826 , G06F9/3834
摘要： A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.
摘要翻译：流水线微处理器包括用于存储转发的电路，通过执行以下操作：对于每个存储请求以及对高速缓存和存储器之一的写入待处理; 获取至少一个完整数据块的最新值; 将存储请求的存储数据与完整的数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的完整数据块缓冲到存储数据队列中; 对于每个加载请求，其中所述加载请求可能需要至少一个更新的完成的数据块：确定在逐块的基础上存储转发是否适合于所述加载请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 并将所选择的数据块转发到加载请求。

45. 发明授权

US08549255B2 Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system 有权
标题翻译：微处理器，方法和计算机程序产品，用于在具有计算机能力的计算机系统中进行直接页面预取
公开(公告)号：US08549255B2
公开(公告)日：2013-10-01
申请号：US12032041
申请日：2008-02-15
申请人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/00
CPC分类号： G06F9/30047 , G06F12/0862
摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.
摘要翻译：配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。提供了一种方法和计算机程序产品。

46. 发明授权

US08285941B2 Enhancing timeliness of cache prefetching 有权
标题翻译：提高缓存预取的及时性
公开(公告)号：US08285941B2
公开(公告)日：2012-10-09
申请号：US12036476
申请日：2008-02-25
申请人： Kattamuri Ekanadham , Jennifer A. Navarro , Il Park , Chung-Lung Kevin Shum
发明人： Kattamuri Ekanadham , Jennifer A. Navarro , Il Park , Chung-Lung Kevin Shum
IPC分类号： G06F12/06
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.
摘要翻译：提供了一种用于增强处理系统中的高速缓存存储器预取的及时性的系统，方法和计算机程序产品。系统包括步幅图案检测器，用于检测作为连续高速缓存访问之间的差异的字节量的步幅大小的步幅图案。系统还包括置信柜台。该系统还包括用于当步幅大小小于高速缓存行大小时执行方法的迫切预取控制逻辑。该方法包括响应于步幅模式检测器检测步幅模式来调整置信计数器，将置信计数器与置信阈值进行比较，以及响应于达到置信阈值的置信度计数器请求高速缓存预取。系统还可以包括选择逻辑以在急切预取控制逻辑和标准步幅预取控制逻辑之间进行选择。

47. 发明授权

US08250336B2 Method, system and computer program product for storing external device result data 失效
标题翻译：用于存储外部设备结果数据的方法，系统和计算机程序产品
公开(公告)号：US08250336B2
公开(公告)日：2012-08-21
申请号：US12036695
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Brian D. Barrick , Thomas Koehler , Aaron Tsai
发明人： Chung-Lung Kevin Shum , Brian D. Barrick , Thomas Koehler , Aaron Tsai
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F9/30043 , G06F9/3824 , G06F9/383 , G06F9/3879
摘要： A method, system, and computer program product for storing result data from an external device. The method includes receiving the result data from the external device, the receiving at a system. The result data is stored into a store data buffer. The store data buffer is utilized by the system to contain store data normally generated by the system. A special store instruction is executed to store the result data into a memory on the system. The special store instruction includes a store address. The executing includes performing an address calculation of the store address based on provided instruction information, and updating a memory location at the store address with contents of the store data buffer utilizing a data path utilized by the system to store data normally generated by the system.
摘要翻译：一种用于从外部设备存储结果数据的方法，系统和计算机程序产品。该方法包括从外部设备接收结果数据，在系统接收。结果数据存储到存储数据缓冲区中。存储数据缓冲器被系统用于包含通常由系统生成的存储数据。执行特殊存储指令以将结果数据存储到系统中的存储器中。特殊商店指令包括商店地址。所述执行包括基于所提供的指示信息执行所述存储地址的地址计算，以及利用所述系统利用的用于存储由所述系统正常生成的数据的数据路径来更新所述存储数据缓冲器的存储位置。

48. 发明授权

US08176301B2 Millicode assist instructions for millicode store access exception checking 有权
标题翻译： Millicode帮助指令用于millicode存储访问异常检查
公开(公告)号：US08176301B2
公开(公告)日：2012-05-08
申请号：US12031756
申请日：2008-02-15
申请人： Mark S. Farrell , Bruce C. Giamei , Chung-Lung Kevin Shum
发明人： Mark S. Farrell , Bruce C. Giamei , Chung-Lung Kevin Shum
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3017 , G06F9/30003 , G06F9/30043 , G06F9/30101 , G06F9/3824 , G06F9/3861
摘要： Millicode store access checking instructions are provided via an operand access control register (OACR) including a test modifier indicator, which is communicatively coupled to an instruction unit subsystem, the instruction unit subsystem for fetching and decoding instructions. The instructions include a millicode instruction with an operand defining an address to check for a store access exception. In addition, an execution unit for executing the millicode instruction performs a method. The method includes receiving the millicode instruction from the instruction unit subsystem, testing for the store access exception at the address as if the test modifier is set absent an update to the OACR, and outputting a result of the testing for the store access exception.
摘要翻译：经由操作数访问控制寄存器（OACR）提供Millicode存储访问检查指令，该操作数访问控制寄存器（OACR）包括通信地耦合到指令单元子系统的指令单元子系统，用于获取和解码指令。该指令包括一个具有操作数的millicode指令，其中定义了一个地址来检查存储访问异常。另外，用于执行millicode指令的执行单元执行一种方法。该方法包括从指令单元子系统接收millicode指令，测试地址处的存储访问异常，就好像将测试修饰符设置为不存在对OACR的更新，并输出用于存储访问异常的测试结果。

49. 发明授权

US08151085B2 Method for address translation in virtual machines 失效
标题翻译：虚拟机地址转换方法
公开(公告)号：US08151085B2
公开(公告)日：2012-04-03
申请号：US12353478
申请日：2009-01-14
申请人： Joerg Deutschle , Ute Gaertner , Erwin Pfeffer , Chung-Lung Kevin Shum , Bruce Wagar
发明人： Joerg Deutschle , Ute Gaertner , Erwin Pfeffer , Chung-Lung Kevin Shum , Bruce Wagar
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/1036 , G06F9/45558 , G06F12/0888 , G06F2009/45583
摘要： The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.
摘要翻译：本发明涉及一种用于运行多级虚拟机的系统中的地址转换方法，该虚拟机包含分层组织的翻译后备缓冲器，其包括至少两个链接的分层子单元，第一子单元包括用于某些更高级地址转换的后备缓冲器并且第二子单元包括用于一些较低级别地址转换级别的后备缓冲器，并且所述第二子单元被布置为将上级子单元的TLB索引地址信息作为标签信息存储在其较低级别的TLB结构中包括以下步骤：在不同的虚拟机级上收集中间的地址转换结果; 并且将中间翻译结果缓冲到翻译后备缓冲器中。

50. 发明授权

US08140951B2 Method and system for instruction address parity comparison 有权
标题翻译：指令地址奇偶校验比较方法和系统
公开(公告)号：US08140951B2
公开(公告)日：2012-03-20
申请号：US12031732
申请日：2008-02-15
申请人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
发明人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/10
摘要： A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing circuitry. The method also includes receiving the distributed instruction address parity value from the one or more functional units, and calculating a completing instruction address (CIA) parity value associated with completing the instruction. The method further includes generating an error indicator in response to a mismatch between the received instruction address parity value and the CIA parity value.
摘要翻译：提供了一种用于指令地址奇偶校验比较的方法和系统。该方法包括计算指令的指令地址奇偶校验值，并将指令地址奇偶校验值分配给处理电路中的一个或多个功能单元。该方法还包括从一个或多个功能单元接收分布式指令地址奇偶校验值，以及计算与完成指令相关联的完成指令地址（CIA）奇偶校验值。该方法还包括响应于接收到的指令地址奇偶校验值和CIA奇偶校验值之间的不匹配而产生错误指示符。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式