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41. 发明申请

US20110086476A1 Methods of Forming Field Effect Transistors on Substrates 有权
标题翻译：在基片上形成场效应晶体管的方法
公开(公告)号：US20110086476A1
公开(公告)日：2011-04-14
申请号：US12969418
申请日：2010-12-15
申请人： Robert J. Hanson , Sanh D. Tang
发明人： Robert J. Hanson , Sanh D. Tang
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/26513 , H01L21/823418 , H01L21/823437 , H01L21/823487 , H01L29/6659 , H01L29/66621 , H01L29/7834
摘要： The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成场效应晶体管的方法。在一个实施方案中，本发明包括在衬底上形成场效应晶体管的方法，其中场效应晶体管包括一对导电掺杂的源极/漏极区域，在该对源极/漏极区域之间接收的沟道区域，以及晶体管栅极可靠地接收在沟道区域。这种实现包括在沉积材料之前对该对源极/漏极区进行掺杂剂激活退火，从而制造晶体管栅极的导电部分。考虑了其他方面和实现。

42. 发明申请

US20100254186A1 METHODS, DEVICES, AND SYSTEMS RELATING TO MEMORY CELLS HAVING A FLOATING BODY 有权
标题翻译：相关于具有浮动体的记忆细胞的方法，装置和系统
公开(公告)号：US20100254186A1
公开(公告)日：2010-10-07
申请号：US12419658
申请日：2009-04-07
申请人： Sanh D. Tang
发明人： Sanh D. Tang
IPC分类号： G11C7/00 , H01L29/66 , H01L21/336
CPC分类号： H01L29/7841 , H01L27/108 , H01L27/10802
摘要： Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a source each formed in silicon and a gate positioned between the drain and the source. The memory cell may further include a bias gate recessed into the silicon and positioned between an isolation region and the transistor. In addition, the bias gate may be configured to be operably coupled to a bias voltage. The memory cell may also include a floating body within the silicon. The floating body may include a first portion adjacent the source and the drain and vertically offset from the bias gate and a second portion coupled to the first portion. Moreover, the bias gate may be formed adjacent to the second portion.
摘要翻译：公开了涉及具有浮体的存储单元的方法，装置和系统。存储单元包括晶体管，其包括各自形成在硅中的漏极和源极以及位于漏极和源极之间的栅极。存储单元还可以包括凹入硅中并且位于隔离区域和晶体管之间的偏置栅极。此外，偏置栅极可以被配置为可操作地耦合到偏置电压。存储单元还可以包括硅内的浮体。浮体可以包括邻近源极和漏极的第一部分，并且垂直偏离偏置栅极，第二部分耦合到第一部分。此外，偏置栅极可以形成为与第二部分相邻。

43. 发明申请

US20100246285A1 METHODS, DEVICES, AND SYSTEMS RELATING TO A MEMORY CELL HAVING A FLOATING BODY 有权
标题翻译：与具有浮动体的记忆体相关的方法，装置和系统
公开(公告)号：US20100246285A1
公开(公告)日：2010-09-30
申请号：US12410207
申请日：2009-03-24
申请人： Sanh D. Tang , Mike N. Nguyen
发明人： Sanh D. Tang , Mike N. Nguyen
IPC分类号： G11C7/00 , H01L27/12 , H01L21/84
CPC分类号： H01L27/10802 , H01L27/1203 , H01L29/66833 , H01L29/7841
摘要： Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer and including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage and extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell includes a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.
摘要翻译：公开了具有浮体的存储单元的方法，装置和系统。存储单元可以包括绝缘层上的晶体管，并且包括源极和漏极。存储单元还可以包括浮动体，其包括位于源极和漏极之间的第一区域，远离源极和漏极中的每一个定位的第二区域，以及通过并延伸穿过绝缘层的第二区域，并将第一区域耦合到第二区。另外，存储器单元包括偏置栅极，至少部分地围绕第二区域并被配置为可操作地耦合到偏置电压。此外，存储单元可以包括多个电介质层，其中第二区域的每个外部垂直表面具有与其相邻的多个电介质层。

44. 发明授权

US07470576B2 Methods of forming field effect transistor gate lines 有权
标题翻译：形成场效应晶体管栅极线的方法
公开(公告)号：US07470576B2
公开(公告)日：2008-12-30
申请号：US11000786
申请日：2004-11-30
申请人： Sanh D. Tang , Michael P. Violette , Robert Burke
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： H01L21/8234
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

45. 发明申请

US20080061346A1 One-transistor memory cell with bias gate 有权
标题翻译：具有偏置栅极的单晶体管存储单元
公开(公告)号：US20080061346A1
公开(公告)日：2008-03-13
申请号：US11516814
申请日：2006-09-07
申请人： Sanh D. Tang , Gordon Haller , Daniel H. Doyle
发明人： Sanh D. Tang , Gordon Haller , Daniel H. Doyle
IPC分类号： H01L29/76 , G11C11/24 , G11C11/34
CPC分类号： H01L29/7841 , G11C11/401 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10844
摘要： One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.
摘要翻译：单晶体管（1T）无电容器DRAM单元各自包括具有将浮体区域与基底基板分离的偏置栅极层的MOS晶体管。 MOS晶体管用作存储器件，不需要存储电容器。通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子他们在哪里举行。

46. 发明授权

US07271086B2 Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces 有权
公开(公告)号：US07271086B2
公开(公告)日：2007-09-18
申请号：US11218254
申请日：2005-09-01
申请人： Sanh D. Tang , Troy Gugel , John Lee , Fred Fishburn
发明人： Sanh D. Tang , Troy Gugel , John Lee , Fred Fishburn
IPC分类号： H01L21/4763
CPC分类号： H01L23/3114 , H01L24/05 , H01L24/11 , H01L24/12 , H01L2224/0231 , H01L2224/02311 , H01L2224/0401 , H01L2224/04073 , H01L2224/05082 , H01L2224/05181 , H01L2224/0558 , H01L2224/05624 , H01L2224/05647 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes constructing a dielectric structure on a microfeature workpiece having a substrate and a terminal carried by the substrate, and removing a section of the dielectric structure to form an opening. The opening has a first portion extending through the dielectric structure and exposing the terminal and a second portion extending to an intermediate depth in the dielectric structure. The second portion is spaced laterally apart from the terminal. The method further includes forming a conductive layer on the microfeature workpiece with the conductive layer in electrical contact with the terminal and disposed in the first and second portions of the opening.

47. 发明授权

US07244659B2 Integrated circuits and methods of forming a field effect transistor 有权
标题翻译：集成电路和形成场效应晶体管的方法
公开(公告)号：US07244659B2
公开(公告)日：2007-07-17
申请号：US11076774
申请日：2005-03-10
申请人： Sanh D. Tang , Gordon Haller
发明人： Sanh D. Tang , Gordon Haller
IPC分类号： H01L21/76
CPC分类号： H01L29/0653 , H01L21/0237 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.
摘要翻译：公开了形成场效应晶体管的集成电路和方法。在一个方面，集成电路包括包括本体半导体材料的半导体衬底。电绝缘材料容纳在本体半导体材料内。在绝缘材料上形成半导体材料。包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。公开了其他方面和实施方式，包括方法方面。

48. 发明授权

US06727150B2 Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers 有权
标题翻译：在包括具有间隔物的T形沟槽的半导体衬底内形成沟槽隔离的方法
公开(公告)号：US06727150B2
公开(公告)日：2004-04-27
申请号：US10206171
申请日：2002-07-26
申请人： Sanh D. Tang
发明人： Sanh D. Tang
IPC分类号： H01L21336
CPC分类号： H01L21/823481 , H01L21/76229
摘要： A method of forming trench isolation within a semiconductor substrate includes forming a first isolation trench of a first open dimension within a semiconductor substrate. The first isolation trench has a base. A second isolation trench is formed into the semiconductor substrate through the base of the first isolation trench. The second isolation trench has a second open dimension along a line parallel with the first open dimension which is less than the first open dimension. Insulative isolation material is formed within the first and second isolation trenches. The insulative isolation material has a void therein extending from within the second isolation trench to the first isolation trench. Other aspects and implementations are contemplated.
摘要翻译：在半导体衬底内形成沟槽隔离的方法包括在半导体衬底内形成第一开口尺寸的第一隔离沟槽。第一隔离槽具有基座。第二隔离沟槽通过第一隔离沟槽的基底形成到半导体衬底中。第二隔离沟槽沿着与第一开放尺寸平行的线具有小于第一开放尺寸的第二开口尺寸。绝缘隔离材料形成在第一和第二隔离沟槽内。绝缘隔离材料具有从第二隔离沟槽内延伸到第一隔离沟槽的空隙。考虑了其他方面和实现。

49. 发明授权

US06693025B2 Local interconnect structures for integrated circuits and methods for making the same 失效
标题翻译：用于集成电路的局部互连结构及其制造方法
公开(公告)号：US06693025B2
公开(公告)日：2004-02-17
申请号：US09943994
申请日：2001-08-30
申请人： Sanh D. Tang , Michael P. Violette
发明人： Sanh D. Tang , Michael P. Violette
IPC分类号： H01L2128
CPC分类号： G01R31/3648 , G01R31/3665 , H01L21/76895 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. The local metal silicide interconnect structure may overlie the at least one gate structure. The methods better protect underlying silicon regions (e.g., substrate), as well as form TiSix local interconnects with good step coverage. Intermediate and resulting structures are also disclosed.
摘要翻译：一种制造柔性金属硅化物局部互连结构的方法。该方法包括在包括至少一个栅极结构的衬底上形成非晶或多晶硅层，在硅层上形成氮化硅层，去除氮化硅层的一部分，氧化硅层的暴露部分，去除氮化硅层的剩余部分，任选地去除氧化硅层，在所得结构上形成金属层，在包含氮的气氛中退火金属层，并去除任何金属氮化物区域。局部金属硅化物互连结构可以覆盖至少一个栅极结构。这些方法更好地保护底层硅区域（例如底层），以及形成具有良好阶梯覆盖的TiSix局部互连。还公开了中间和结构的结构。

50. 发明授权

US06352916B1 Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench 失效
标题翻译：通过从沟槽部分去除导电材料在多层互连结构中形成插塞的方法
公开(公告)号：US06352916B1
公开(公告)日：2002-03-05
申请号：US09432516
申请日：1999-11-02
申请人： Sanh D. Tang , Rajendra Narasimhan
发明人： Sanh D. Tang , Rajendra Narasimhan
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76834 , H01L21/76883 , H01L21/76885 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, a conductive structure comprising an interconnect and an overlying plug integrally extending therefrom is provided. The structure can be provided by a damascene process, wherein an opening is defined in insulation deep enough to accommodate the height of an interconnect and its overlying plug. The opening is filled with metal, and non-plug areas of the metal are then recessed down to a standard interconnect height within the trench. The full height of the metal is retained at the plug site. Oxide is then deposited over the recessed portions. Alternatively, a continuous metal layer is provided that is deep enough to accommodate the height of an interconnect and its overlying plug. The metal is then etched to form the interconnect/plug structure, and insulation is deposited thereover. Multiple structures may be provided at the same level using these processes, and multiple levels of these structures may be similarly provided.
摘要翻译：在半导体器件中，提供了包括互连的导电结构和从其整体延伸的上覆插塞。该结构可以通过镶嵌工艺来提供，其中开口被限定在绝缘层中足够深以适应互连件及其上覆塞子的高度。开口填充有金属，然后金属的非插塞区域向下凹陷到沟槽内的标准互连高度。金属的全高度保留在插塞位置。然后将氧化物沉积在凹陷部分上。或者，提供足够深的连续金属层以适应互连件及其上覆插头的高度。然后蚀刻金属以形成互连/插塞结构，并在其上沉积绝缘体。可以使用这些过程在同一级别提供多个结构，并且可以类似地提供这些结构的多个级别。

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