专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

WO2013078069A1 3D NON-VOLATILE MEMORY WITH METAL SILICIDE INTERCONNECT 审中-公开
标题翻译：具有金属硅化物互连的3D非易失性存储器
公开(公告)号：WO2013078069A1
公开(公告)日：2013-05-30
申请号：PCT/US2012/065375
申请日：2012-11-15
申请人： SANDISK TECHNOLOGIES, INC. , HIGASHITANI, Masaaki , RABKIN, Peter
发明人： HIGASHITANI, Masaaki , RABKIN, Peter
IPC分类号： H01L27/115 , H01L23/532
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/06 , H01L23/53209 , H01L27/11519 , H01L27/11531 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： A stacked non-volatile memory cell array include cell areas (CA3,4) with rows of vertical columns of NAND cells, and an interconnect area (IA1), e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect (I1, I2) extending between insulation-filled slits (S5, S6, S7), and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.
摘要翻译：堆叠的非易失性存储单元阵列包括具有NAND单元的垂直列行的单元区域（CA3,4），以及例如阵列中途并且延伸阵列的长度的互连区域（IA1）。互连区域包括在绝缘填充的狭缝（S5，S6，S7）之间延伸的至少一个金属硅化物互连（I1，I2），并且不包括NAND单元的垂直列。金属硅化物互连可以将电力和控制信号从堆叠下方传递到堆叠之上。金属硅化物互连也可以形成在衬底的周边区域中。接触结构可以从互连的梯形部分延伸到堆叠之上的至少一个上金属层，以完成从堆叠下方的电路到上金属层的导电路径。可以在阵列的平面中提供子阵列，而不需要字线连接和子阵列之间的传输区域。

42. 发明申请

WO2012047745A1 A METHOD OF PATTERNING NAND STRINGS USING PERPENDICULAR SRAF 审中-公开
标题翻译：使用PERPENDICULAR SRAF绘制NAND条的方法
公开(公告)号：WO2012047745A1
公开(公告)日：2012-04-12
申请号：PCT/US2011/054181
申请日：2011-09-30
申请人： SANDISK TECHNOLOGIES INC. , HUANG, Chenche , WANG, Chun-Ming , HIGASHITANI, Masaaki
发明人： HUANG, Chenche , WANG, Chun-Ming , HIGASHITANI, Masaaki
IPC分类号： G03F1/36
CPC分类号： G03F1/36
摘要： A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate.
摘要翻译：光刻掩模包括形成在掩模基板上的多个图案化特征以及基本上垂直于掩模基板上的图案化特征形成的第一多个次分辨率辅助特征（SRAF）。

43. 发明申请

WO2014066263A1 DYNAMIC BIT LINE BIAS FOR PROGRAMMING NON-VOLATILE MEMORY 审中-公开
标题翻译：用于编程非易失性存储器的动态位线偏移
公开(公告)号：WO2014066263A1
公开(公告)日：2014-05-01
申请号：PCT/US2013/065969
申请日：2013-10-21
申请人： SANDISK TECHNOLOGIES,INC. , DUTTA, Deepanshu , OOWADA, Ken , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： DUTTA, Deepanshu , OOWADA, Ken , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C11/56 , G11C16/12 , G11C7/12 , G11C16/24
CPC分类号： G11C16/10 , G11C7/12 , G11C11/5628 , G11C16/12 , G11C16/24 , G11C16/3459
摘要： A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.
摘要翻译：用于一组非易失性存储元件的程序操作。维持以慢编程模式施加到单个存储元件的多个编程脉冲的计数，并且基于计数调整相关联的位线电压。可以使用不同的位线电压，具有公共的步长或不同的步长。结果，缓慢编程模式下的存储元件的阈值电压的变化可以使每个编程脉冲均匀，从而提高编程精度。在缓慢编程模式下，锁存器保持相关存储元件所经历的编程脉冲计数。当其阈值电压低于较低验证电平时，存储元件处于快速编程模式，而当其阈值电压处于较低验证电平和较高验证电平之间时，存储元件处于慢速编程模式。

44. 发明申请

WO2013180893A1 THRESHOLD VOLTAGE ADJUSTMENT FOR A SELECT GATE TRANSISTOR IN A STACKED NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：堆叠非易失性存储器件中的选择栅极晶体管的阈值电压调整
公开(公告)号：WO2013180893A1
公开(公告)日：2013-12-05
申请号：PCT/US2013/039505
申请日：2013-05-03
申请人： SANDISK TECHNOLOGIES, INC. , LI, Haibo , COSTA, Xiying , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： LI, Haibo , COSTA, Xiying , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C29/02 , G11C16/04
CPC分类号： G11C16/0483 , G11C29/025 , G11C29/028
摘要： In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.
摘要翻译：在3D堆叠的非易失性存储器件中，对串联存储器单元串的漏极端的选择栅极，漏极（SGD）晶体管评估和调整阈值电压。为了优化和紧固阈值电压分布，SGD晶体管在可接受范围的较低和较高电平下读取。具有低阈值电压的SGD晶体管进行编程，并且具有高阈值电压的SGD晶体管将被擦除，以使阈值电压达到可接受的范围。可以重复评估和调整，例如在相关子块的指定数量的编程擦除周期之后。重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。方面包括通过验证和抑制来编程SGD晶体管，擦除具有验证和抑制的SGD晶体管，以及上述两者。

45. 发明申请

WO2013158557A1 ERASE OPERATION FOR 3D NON VOLATILE MEMORY WITH CONTROLLABLE GATE-INDUCED DRAIN LEAKAGE CURRENT 审中-公开
标题翻译：具有可控门控感应漏水电流的3D非易失性存储器的擦除操作
公开(公告)号：WO2013158557A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/036616
申请日：2013-04-15
申请人： SANDISK TECHNOLOGIES, INC. , COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
发明人： COSTA, Xiying , LI, Haibo , HIGASHITANI, Masaaki , MUI, Man, L.
IPC分类号： G11C16/06 , G11C5/02 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate- induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
摘要翻译：用于3D堆叠存储器件的擦除操作将包括中间电平（Vgid1）和峰值电平（Verase）的擦除脉冲施加到一组存储器单元，并且在擦除操作的擦除迭代中对Vgid1进行升压。当指定部分的单元格已达到擦除验证级别时，可以升级Vgidl。在这种情况下，大多数单元可能已经达到擦除验证电平，使得剩余的单元可以受益于更高的栅极引起的漏极泄漏（GIDL）电流以达到擦除验证电平。 Verase可以在Vigdl加强之前，可选地升级，但在Vgidl步进时保持固定。 Vgidl可以升高直到达到最大允许电平Vgidl_max。 Vgid1可以分别经由位线或源极线施加到NAND串的漏极侧和/或源极侧。

46. 发明申请

WO2013155332A1 THIN FILM TRANSISTOR 审中-公开
标题翻译：薄膜晶体管
公开(公告)号：WO2013155332A1
公开(公告)日：2013-10-17
申请号：PCT/US2013/036217
申请日：2013-04-11
申请人： SANDISK TECHNOLOGIES, INC. , RABKIN, Peter , HIGASHITANI, Masaaki
发明人： RABKIN, Peter , HIGASHITANI, Masaaki
IPC分类号： H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L29/66757 , G11C16/0483 , G11C16/06 , G11C16/08 , H01L21/02532 , H01L21/02595 , H01L21/04 , H01L21/26513 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L27/1222 , H01L27/1259 , H01L29/42384 , H01L29/66477 , H01L29/66742 , H01L29/6675 , H01L29/66787 , H01L29/785 , H01L29/78642 , H01L29/78696 , H01L29/7926
摘要： Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. An interface between the gate electrode and gate dielectric may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. The TFT may have a channel width that is defined by a thickness of the horizontal layer of polysilicon. The TFT may be formed by etching a hole in a layer of polysilicon. Then, a gate electrode and gate dielectric may be formed in the hole by depositing layers of dielectric and conductor material on the sidewall. The body may be formed in the horizontal layer of polysilicon outside the hole.
摘要翻译：本文公开了薄膜晶体管（TFT）和用于制造TFT的技术。 TFT的栅电极的主平面可以相对于TFT所在的水平多晶硅层垂直取向。栅极电极和栅极电介质之间的界面可以相对于TFT所在的水平多晶硅层垂直取向。 TFT可以具有由多晶硅的水平层的厚度限定的沟道宽度。 TFT可以通过蚀刻多晶硅层中的孔而形成。然后，可以通过在侧壁上沉积电介质和导体材料层而在孔中形成栅极电极和栅极电介质。主体可以形成在孔外的多晶硅的水平层中。

47. 发明申请

WO2013078068A1 PASSIVE DEVICES FOR 3D NON-VOLATILE MEMORY 审中-公开
标题翻译：用于3D非易失性存储器的被动设备
公开(公告)号：WO2013078068A1
公开(公告)日：2013-05-30
申请号：PCT/US2012/065374
申请日：2012-11-15
申请人： SANDISK TECHNOLOGIES, INC. , HIGASHITANI, Masaaki , RABKIN, Peter
发明人： HIGASHITANI, Masaaki , RABKIN, Peter
IPC分类号： H01L27/115 , H01L27/06 , H01L23/522 , H01L49/02
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11531 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L28/87
摘要： Passive devices such as resistors and capacitors are provided for a 3D non-volatile memory device. In a peripheral area of a substrate, a passive device includes alternating layers of a dielectric (L0, L2,...,L12) such as oxide and a conductive material (L1, L3,...,L13) such as heavily doped polysilicon or metal silicide in a stack. The substrate includes one or more lower metal layers (M1) connected to circuitry. One or more upper metal layers (DO) are provided above the stack. Contact structures (2802...2814) extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel, for a capacitor, or serially, for a resistor, by the contact structures and the at least one upper metal layer. Additional contact structures (2906, 2908) can connect the circuitry to the one or more upper metal layers.
摘要翻译：为三维非易失性存储器件提供诸如电阻器和电容器的无源器件。在基板的周边区域中，无源器件包括诸如氧化物和导电材料（L1，L3，...，L13）的电介质（L0，L2，...，L12）的交替层，例如重掺杂堆叠中的多晶硅或金属硅化物。衬底包括连接到电路的一个或多个下金属层（M1）。在堆叠上方提供一个或多个上金属层（DO）。接触结构（2802 ... 2814）从导电材料层延伸到一个或多个上金属层的部分，使得导电材料层彼此并联连接，用于电容器或串联连接，用于电阻器，通过接触结构和至少一个上金属层。附加接触结构（2906,2908）可以将电路连接到一个或多个上金属层。

48. 发明申请

WO2013062936A1 BACK-BIASING WORD LINE SWITCH TRANSISTORS 审中-公开
标题翻译：反向偏移字线开关晶体管
公开(公告)号：WO2013062936A1
公开(公告)日：2013-05-02
申请号：PCT/US2012/061421
申请日：2012-10-23
申请人： SANDISK TECHNOLOGIES, INC. , TOYAMA, Fumiaki , HIGASHITANI, Masaaki
发明人： TOYAMA, Fumiaki , HIGASHITANI, Masaaki
IPC分类号： G11C16/04 , G11C16/08
CPC分类号： G11C16/0483 , G11C16/08
摘要： Back biasing word line switch transistors is disclosed. One embodiment includes word line switch transistors that are in a well in a substrate. A memory array having non-volatile storage devices may be in a separate well in the substrate. The well of the word line switch transistors may be biased separately from the well of the non-volatile storage devices. While programming the non-volatile storage devices, a negative voltage may be applied to the well of the word line switch transistors. This may reduce the voltage that needs to be applied to the gate of a WL switch transistor to pass the program voltage to the selected word line. Therefore, charge pumps can be made smaller, since the maximum voltage they need to generate is smaller. A word line switch transistor may be back-biased during a read operation to pass a negative read compare voltage to a selected word line.
摘要翻译：公开了背偏置字线开关晶体管。一个实施例包括位于衬底中的阱中的字线开关晶体管。具有非易失性存储装置的存储器阵列可以在衬底中的单独的阱中。字线开关晶体管的阱可以与非易失性存储器件的阱分开偏置。在对非易失性存储设备进行编程时，可以向字线开关晶体管的阱施加负电压。这可以降低需要施加到WL开关晶体管的栅极的电压，以将编程电压传递到所选择的字线。因此，可以使电荷泵更小，因为它们需要产生的最大电压较小。在读取操作期间，字线开关晶体管可以被反向偏置，以将负的读取比较电压传递到所选择的字线。

49. 发明申请

WO2013043602A2 HIGH ENDURANCE NON-VOLATILE STORAGE 审中-公开
标题翻译：高耐久性非挥发性储存
公开(公告)号：WO2013043602A2
公开(公告)日：2013-03-28
申请号：PCT/US2012/055919
申请日：2012-09-18
申请人： SANDISK TECHNOLOGIES, INC. , CHEN, Jian , GOROBETS, Sergei , SPROUSE, Steven , KUO, Tien-chien , LI, Yan , LEE, Seungpil , MAK, Alex , DUTTA, Deepanshu , HIGASHITANI, Masaaki
发明人： CHEN, Jian , GOROBETS, Sergei , SPROUSE, Steven , KUO, Tien-chien , LI, Yan , LEE, Seungpil , MAK, Alex , DUTTA, Deepanshu , HIGASHITANI, Masaaki
IPC分类号： G11C16/10 , G11C11/56 , G11C5/06
CPC分类号： G11C16/10 , G11C5/063 , G11C11/5628 , G11C2211/5641
摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
摘要翻译：公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

50. 发明申请

WO2012122188A1 NON-VOLATILE STORAGE ELEMENT COMPRISING A FLOATING GATE WITH A PN JUNCTION AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：包含具有PN结的浮动门的非易失性存储元件及其形成方法
公开(公告)号：WO2012122188A1
公开(公告)日：2012-09-13
申请号：PCT/US2012/027920
申请日：2012-03-06
申请人： SANDISK TECHNOLOGIES, INC. , DUNGA, Mohan , LEE, Sanghyun , HIGASHITANI, Masaaki , PHAM, Tuan
发明人： DUNGA, Mohan , LEE, Sanghyun , HIGASHITANI, Masaaki , PHAM, Tuan
IPC分类号： H01L21/28 , H01L21/8247 , H01L29/788 , H01L27/115 , G11C16/04 , H01L29/423 , H01L21/8234
CPC分类号： H01L29/66825 , G11C11/5642 , G11C16/0408 , G11C16/3418 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/7881
摘要： Non-volatile storage elements having a PN floating gate (811) are disclosed herein. The floating gate has a P- region (804) near the tunnel oxide (805), and may have an N+ region (808) near the control gate (812). In some embodiments, a P- region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P- region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.
摘要翻译：本文公开了具有PN浮动栅极（811）的非易失性存储元件。浮动栅极具有在隧道氧化物（805）附近的P-区域（804），并且可以在控制栅极（812）附近具有N +区域（808）。在一些实施例中，隧道氧化物附近的P-区域有助于提供良好的数据保持。在一些实施例中，控制栅极附近的N +区域有助于实现控制栅极和浮置栅极之间良好的耦合比。因此，非易失性存储元件的编程是有效的。也可以有效地擦除非易失性存储元件。在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式