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41. 发明授权

US6146952A Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof 有权
标题翻译：具有自对准不对称源极/漏极区域的半导体器件及其制造方法
公开(公告)号：US6146952A
公开(公告)日：2000-11-14
申请号：US164836
申请日：1998-10-01
申请人： Homi E. Nariman , H. Jim Fulford , Charles E. May
发明人： Homi E. Nariman , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28114 , H01L29/42376 , H01L29/7835 , H01L29/665
摘要： A semiconductor device and manufacturing method is provided in which asymmetric source/drain regions are formed using a self aligning implant mask. A gate electrode is formed on a substrate and a dielectric layer is formed over the substrate and adjacent the gate electrode. A masking layer is formed over the dielectric layer and the gate electrode and selectively removed to form an implant mask. The implant mask extends further over a first side of the gate electrode than a second side of the gate electrode. Using the implant mask for alignment, a dopant is implanted into the active regions of the substrate adjacent the gate electrode to form a first heavily-doped region adjacent the first side of the gate electrode and second heavily-doped region adjacent the second side of the gate electrode. The first heavily-doped region is spaced further from the gate electrode than the second heavily-doped region. Contacts may be formed to the masking layer or a silicide layer formed from the masking layer.
摘要翻译：提供一种半导体器件和制造方法，其中使用自对准注入掩模形成不对称的源极/漏极区域。在基板上形成栅电极，在基板上形成电介质层，与栅电极相邻。在电介质层和栅电极之上形成掩模层，并选择性地去除以形成植入物掩模。植入掩模在栅电极的第一侧上比栅电极的第二侧进一步延伸。使用注入掩模进行对准，将掺杂剂注入与栅电极相邻的衬底的有源区中，以形成与栅电极的第一侧相邻的第一重掺杂区和与第二重掺杂区相邻的第二重掺杂区栅电极。第一重掺杂区域比栅极电极比第二重掺杂区域更远。可以将掩模层或由掩模层形成的硅化物层形成触点。

42. 发明授权

US06144071A Ultrathin silicon nitride containing sidewall spacers for improved transistor performance 有权
标题翻译：含有超薄氮化硅的侧壁间隔物，用于改善晶体管性能
公开(公告)号：US06144071A
公开(公告)日：2000-11-07
申请号：US146294
申请日：1998-09-03
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/336 , H01L29/49 , H01L29/78 , H01L29/76 , H01L27/088 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6659 , H01L29/4983 , H01L29/6656 , H01L29/7833 , H01L29/665 , Y10S257/90
摘要： A transistor is provided having a pair of sidewall spacers, each preferably including an ultrathin silicon nitride layer, adjacent to opposed sidewall surfaces of a gate conductor on a semiconductor substrate. Each spacer preferably includes a layer of thermally grown silicon nitride, and may also include a silicon dioxide layer. In an embodiment, the spacer includes a first silicon nitride layer adjacent to the sidewall surface, a silicon dioxide layer adjacent to the first silicon nitride layer, and a second silicon nitride layer adjacent to the silicon dioxide layer. Impurity distributions within the substrate may be aligned with any of the layers within the spacer, such that a distribution may be aligned with a sidewall surface or displaced outward from a sidewall surface. Such a distribution may be displaced outward by the lateral width of the spacer or by less than the lateral width of the spacer (i.e. the width of one or more layers within the spacer).
摘要翻译：提供一个晶体管，其具有一对侧壁间隔物，每个侧壁间隔物优选地包括一个超薄氮化硅层，与半导体衬底上的栅极导体的相对的侧壁表面相邻。每个间隔物优选地包括热生长的氮化硅层，并且还可以包括二氧化硅层。在一个实施例中，间隔件包括邻近侧壁表面的第一氮化硅层，与第一氮化硅层相邻的二氧化硅层和与二氧化硅层相邻的第二氮化硅层。衬底内的杂质分布可以与间隔物内的任何层对准，使得分布可与侧壁表面对准或从侧壁表面向外移位。这种分布可以通过间隔物的横向宽度向外移动，或者可以小于间隔物的横向宽度（即间隔物内的一个或多个层的宽度）。

43. 发明授权

US6100173A Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process 失效
标题翻译：形成自对准硅化物栅导体，使其厚度大于使用双重盐析法的连接硅化物结构
公开(公告)号：US6100173A
公开(公告)日：2000-08-08
申请号：US116066
申请日：1998-07-15
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L29/51 , H01L21/3205
CPC分类号： H01L21/28194 , H01L21/28052 , H01L21/28097 , H01L21/28518 , H01L29/517 , H01L29/66507 , H01L29/6659 , H01L29/51
摘要： An integrated circuit fabrication process is provided for using a dual salicidation process to form a silicide gate conductor to a greater thickness than silicide structures formed upon source and drain regions of a transistor. A high K gate dielectric residing between the gate conductor and the substrate substantially inhibits consumption of the junctions during the formation of the silicide gate conductor. In an embodiment, a relatively thick layer of refractory metal is deposited across a transistor arranged upon and within a silicon-based substrate. The transistor includes a polysilicon gate conductor arranged upon a portion of a high K gate dielectric interposed between a pair of source and drain junctions. The refractory metal is heated to convert the polysilicon gate conductor to a silicide gate conductor. After removing the gate dielectric from the source and drain regions, a relatively thin layer of refractory metal is deposited across the topography and heated to form silicide structures upon the source and drain regions.
摘要翻译：提供了一种集成电路制造工艺，其使用双重氧化工艺以形成比形成在晶体管的源极和漏极区域上的硅化物结构更大的厚度的硅化物栅极导体。位于栅极导体和衬底之间的高K栅极电介质在硅化物栅极导体的形成期间基本上抑制了结的消耗。在一个实施例中，相对厚的难熔金属层沉积在布置在硅基衬底上和晶体管内的晶体管上。晶体管包括布置在插入在一对源极和漏极结之间的高K栅极电介质的一部分上的多晶硅栅极导体。将难熔金属加热以将多晶硅栅极导体转换成硅化物栅极导体。在从源极和漏极区域去除栅极电介质之后，将相对薄的难熔金属层跨越形貌沉积并被加热以在源极和漏极区域上形成硅化物结构。

44. 发明授权

US6084280A Transistor having a metal silicide self-aligned to the gate 有权
标题翻译：具有与栅极自对准的金属硅化物的晶体管
公开(公告)号：US6084280A
公开(公告)日：2000-07-04
申请号：US173233
申请日：1998-10-15
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28518 , H01L29/66545
摘要： A transistor having a source/drain metal silicide in close proximity to the channel region may be formed according to the following process. A masking structure is formed upon a semiconductor substrate, and a metal is deposited self-aligned to sidewall surfaces of the masking structure. The metal is then annealed to form a metal silicide. Following formation of lightly doped drain impurity areas self-aligned to the sidewall surfaces of the masking structure, spacers may be formed adjacent the sidewall surfaces and source and drain impurity areas may be formed self-aligned to sidewall surfaces of the spacers. Fill structures are then formed adjacent the spacers and the masking structure is removed to form an opening between the spacers. A gate dielectric is formed upon the exposed upper surface of the semiconductor substrate within the opening, and a gate conductor is formed within the opening. According to one embodiment, the fill structures are removed and an interlevel dielectric is formed upon the transistor. In an alternative embodiment, the fill structures include a dielectric material and are retained as interlevel dielectrics. In a further embodiment, the fill structures include a conductive material and are retained as contacts between the source and drain areas and subsequently formed interconnects. The current transistor may be formed such that the metal silicide is aligned with the gate dielectric and is located in close proximity to the channel region.
摘要翻译：可以根据以下过程形成具有靠近沟道区的源极/漏极金属硅化物的晶体管。在半导体衬底上形成掩模结构，并且将金属沉积自对准到掩模结构的侧壁表面。然后将金属退火以形成金属硅化物。在形成与掩模结构的侧壁表面自对准的轻掺杂漏极杂质区域之后，可以在侧壁表面附近形成间隔物，并且可以将源极和漏极杂质区域形成为自对准到间隔物的侧壁表面。然后在间隔物附近形成填充结构，并且去除掩模结构以在间隔物之间形成开口。在开口内的半导体衬底的暴露的上表面上形成栅极电介质，并且在开口内形成栅极导体。根据一个实施例，去除填充结构，并在晶体管上形成层间电介质。在替代实施例中，填充结构包括电介质材料并保留为层间电介质。在另一个实施例中，填充结构包括导电材料并且被保持为源极和漏极区域之间的接触以及随后形成的互连。电流晶体管可以形成为使得金属硅化物与栅极电介质对准并且位于紧邻沟道区域。

45. 发明授权

US6077749A Method of making dual channel gate oxide thickness for MOSFET transistor design 失效
标题翻译：制造MOSFET晶体管设计的双通道栅氧化层厚度的方法
公开(公告)号：US6077749A
公开(公告)日：2000-06-20
申请号：US34117
申请日：1998-03-03
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/42368 , H01L29/518 , H01L29/66583 , Y10S438/981
摘要： A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. The oxide having the greater thickness is formed adjacent a source or drain region of the device, and the oxide with the lesser thickness is formed adjacent the other one of the source or drain regions. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO.sub.2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO.sub.2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.
摘要翻译：具有第一厚度和第二厚度的栅极氧化物的半导体器件通过首先用氮离子注入半导体衬底的栅极区域的一部分，然后在栅极区域上形成栅极氧化物来形成。具有较大厚度的氧化物邻近器件的源极或漏极区域形成，并且具有较小厚度的氧化物形成为邻近源极或漏极区域中的另一个。优选地，通过将栅极区域暴露于氧气环境来生长栅极氧化物。氮注入抑制氧气环境中的二氧化硅生长速率。因此，具有植入氮原子的栅极区域的部分将生长或形成诸如SiO 2的栅极氧化物层，其比栅极区域较少注入或未注入氮原子的部分更薄。可以沉积栅极氧化物层而不是生长栅极氧化物层。在形成栅极氧化物层之后，将多晶硅沉积到栅极氧化物上。然后可以注入半导体衬底以形成掺杂的漏极和源极区域。然后可以将间隔物放置在漏极和源极区域上并且邻近栅极的侧壁的端部。

46. 发明授权

US6063679A Spacer formation for graded dopant profile having a triangular geometry 失效
标题翻译：具有三角形几何形状的分级掺杂剂分布的间隔物形成
公开(公告)号：US6063679A
公开(公告)日：2000-05-16
申请号：US987558
申请日：1997-12-09
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/266 , H01L21/336
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/6659
摘要： The formation of a spacer for a graded dopant profile having a triangular geometry is disclosed. In one embodiment, a method has three steps. In the first step, a gate is formed on a substrate, the gate having two edges. In the second step, at least one spacer is formed, where each spacer is adjacent to an edge of the gate and has a triangular geometry. In the third step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer.
摘要翻译：公开了用于具有三角形几何形状的渐变掺杂剂分布的间隔物的形成。在一个实施例中，方法具有三个步骤。在第一步骤中，栅极形成在衬底上，栅极具有两个边缘。在第二步骤中，形成至少一个间隔件，其中每个间隔件邻近门的边缘并具有三角形几何形状。在第三步骤中，施加离子注入以在每个间隔物下面的衬底内形成渐变的轻掺杂区域，该区域对应于间隔物的三角形几何形状。

47. 发明授权

US06046089A Selectively sized spacers 失效
标题翻译：选择尺寸的垫片
公开(公告)号：US06046089A
公开(公告)日：2000-04-04
申请号：US2727
申请日：1998-01-05
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/311 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/31116
摘要： The formation of selectively sized spacers is disclosed. One embodiment comprises a method including four steps. In the first step, at least one spacer for each of a plurality of gates is formed on a substrate, the plurality of gates including a first gate and at least one remaining gate, and each spacer adjacent to an edge of its corresponding gate. In the second step, a mask is applied to the first gate, including the spacers for the first gate. In the third step, the spacers for the remaining gates are etched. In the fourth step, the mask applied to the first gate, including the spacers for the first gate, is removed.
摘要翻译：公开了选择性尺寸的间隔物的形成。一个实施例包括一个包括四个步骤的方法。在第一步骤中，在衬底上形成用于多个栅极中的每一个的至少一个间隔物，所述多个栅极包括第一栅极和至少一个剩余栅极，并且每个间隔物邻近其对应栅极的边缘。在第二步骤中，将掩模施加到第一栅极，包括用于第一栅极的间隔物。在第三步骤中，蚀刻用于剩余栅极的间隔物。在第四步骤中，去除了包括用于第一栅极的间隔物的第一栅极的掩模。

48. 发明授权

US5943585A Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen 失效
标题翻译：沟槽隔离结构，其具有布置在掺入氮气的氧化物衬垫上的低K电介质间隔物
公开(公告)号：US5943585A
公开(公告)日：1999-08-24
申请号：US994253
申请日：1997-12-19
申请人： Charles E. May , Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Charles E. May , Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76237
摘要： A process is provided for forming a trench isolation structure which includes dielectric spacers composed of a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. In an embodiment, a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner which is incorporated with nitrogen atoms is thermally grown upon the sidewalls and base of the trench. A layer of low K dielectric material is deposited across the oxide liner and the masking layer. The dielectric material is anisotropically etched to form sidewall spacers upon the oxide liner. A fill oxide is then formed within the trench upon the sidewall spacers and the oxide liner. The resulting trench isolation structure includes a low K dielectric material interposed between an oxide liner and a fill oxide. The trench isolation structure is less is likely to experience current leakage during the operation of an ensuing integrated circuit employing the isolation structure.
摘要翻译：提供了一种用于形成沟槽隔离结构的工艺，该沟槽隔离结构包括由介电材料构成的电介质隔离层，介电材料具有相对低的介电常数K，大约小于3.8。由沟槽隔离结构隔开的与K成正比的有源区之间的电容因此减小。在一个实施例中，在形成有掩模层的半导体衬底内蚀刻沟槽。掺有氮原子的氧化物衬垫在沟槽的侧壁和基底上热生长。一层低K电介质材料沉积在氧化物衬垫和掩蔽层两侧。电介质材料被各向异性地蚀刻以在氧化物衬垫上形成侧壁间隔物。然后在沟槽内在侧壁间隔物和氧化物衬垫上形成填充氧化物。所形成的沟槽隔离结构包括介于氧化物衬垫和填充氧化物之间的低K电介质材料。在采用隔离结构的随后的集成电路的操作期间，沟槽隔离结构较少可能经历电流泄漏。

49. 发明授权

US5915195A Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure 失效
标题翻译：离子注入工艺，以改善浅沟槽隔离结构边缘处的栅氧化层质量
公开(公告)号：US5915195A
公开(公告)日：1999-06-22
申请号：US977795
申请日：1997-11-25
申请人： H. Jim Fulford, Jr. , Charles E. May
发明人： H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/76 , H01L21/28 , H01L21/316 , H01L21/762 , H01L29/423 , H01L29/51 , H01L29/78 , H01L21/265
CPC分类号： H01L21/28202 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L21/76235 , H01L21/76237 , H01L29/42368 , H01L29/518
摘要： A semiconductor fabrication process comprising forming a dielectric on an upper surface of a single crystal silicon substrate. A trench mask is then patterned on an upper surface of the dielectric. The trench mask exposes portions of the dielectric situated over portions of the isolation region. Exposed portions of the dielectric are then removed and portions of the silicon within the isolation region are also removed to form an isolation trench within the silicon substrate. This formation results in the formation of corners in the silicon substrate where the upper surface of the silicon substrate intersects with sidewalls of the isolation trench. Localized damage is then created in regions proximal to these corners of the silicon substrate preferably through the use of one or more ion implantation processes performed at implant angles in excess of approximately 30.degree. C. During the subsequent formation of a liner oxide on the sidewalls and floor of the isolation trench, the localized damage region results in a higher oxidation rate of the silicon substrate proximal to the silicon substrate corners. This higher oxidation rate results in a rounding or smoothing of the silicon corners thereby resulting in a less severe gradient between the silicon active region and the isolation trench.
摘要翻译：一种半导体制造工艺，包括在单晶硅衬底的上表面上形成电介质。然后在电介质的上表面上形成沟槽掩模。沟槽掩模暴露位于隔离区域的部分之上的电介质的部分。然后去除电介质的暴露部分，并且去除隔离区内的硅的部分，以在硅衬底内形成隔离沟槽。这种形成导致硅衬底中的角部的形成，其中硅衬底的上表面与隔离沟槽的侧壁相交。然后在硅衬底的这些角部附近的区域中产生局部损伤，优选地通过使用在超过约30℃的植入角度下进行的一个或多个离子注入工艺。在随后在侧壁上形成衬垫氧化物隔离沟槽的地板，局部损伤区域导致硅衬底接近硅衬底拐角的较高的氧化速率。这种较高的氧化速率导致硅角的倒圆或平滑，从而导致硅有源区和隔离沟之间的较不严格的梯度。

50. 发明授权

US07436040B2 Method and apparatus for diverting void diffusion in integrated circuit conductors 有权
标题翻译：用于在集成电路导体中转移空穴扩散的方法和装置
公开(公告)号：US07436040B2
公开(公告)日：2008-10-14
申请号：US11323398
申请日：2005-12-29
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L23/58
CPC分类号： H01L21/7682 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
摘要翻译：在集成电路中转移空穴扩散的方法包括以下步骤：在集成电路的第一导电层中形成具有边界的电导体，在电介质层的边界内在第一导电层和第二导电层，并且在电导体的通孔和边界之间形成槽，用于将电导体中的空隙扩散转移离开通孔。

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