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41. 发明授权

US6166427A Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application 有权
标题翻译：将低K SiOF作为层间电介质的集成应用于AL间隙填充
公开(公告)号：US6166427A
公开(公告)日：2000-12-26
申请号：US231649
申请日：1998-01-15
申请人： Richard J. Huang , John A. Iacoponi
发明人： Richard J. Huang , John A. Iacoponi
IPC分类号： C23C16/40 , H01L21/316 , H01L21/768 , H01L23/532 , H01L23/58 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02274 , H01L21/02332 , H01L21/02362 , H01L21/31629 , H01L21/76801 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76835 , H01L21/76837 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a dielectric layer in a semiconductor product includes two steps. The first step is forming a fluorinated layer (e.g. SiOF or fluorosilicate glass ("FSG")) which includes a material formed in part with fluorine. The second step is forming a fill layer (e.g. SiO.sub.2) above the fluorinated layer. The fill layer is substantially free of materials formed in part with fluorine. A top surface of the fill layer can be planarized. Surface treatments and oxide caps can be applied to the planarized surface to form fluorine barriers if part of the fluorinated layer is exposed to higher layers. Such a method, and a semiconductor device or integrated circuit manufactured according to the method, allow the dielectric constant of an inter-layer dielectric ("ILD") to be lowered while also minimizing the complexity and expense of the manufacturing process.
摘要翻译：半导体产品中的介电层的制造方法包括两个步骤。第一步是形成氟化层（例如SiOF或氟硅酸盐玻璃（“FSG”），其包括部分由氟形成的材料。第二步是在氟化层之上形成填充层（例如SiO 2）。填充层基本上不含部分由氟形成的材料。填充层的顶表面可以被平坦化。如果氟化层的一部分暴露于较高层，则表面处理和氧化物盖可以施加到平坦化表面以形成氟阻挡层。这样的方法以及根据该方法制造的半导体器件或集成电路能够降低层间电介质（“ILD”）的介电常数，同时也使制造工艺的复杂性和费用最小化。

42. 发明授权

US6011289A Metal oxide stack for flash memory application 有权
标题翻译：用于闪存应用的金属氧化物堆叠
公开(公告)号：US6011289A
公开(公告)日：2000-01-04
申请号：US154073
申请日：1998-09-16
申请人： Richard J. Huang , Lewis Shen
发明人： Richard J. Huang , Lewis Shen
IPC分类号： H01L21/28 , H01L29/423 , H01L29/49 , H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/4975
摘要： In order to alleviate lifting problems and to reduce the height of the stack, a tungsten layer is formed on a interpoly dielectric layer, such as an ONO layer, which separates the conductive control gate from a polysilicon floating gate that is in turn formed on a tunnel oxide layer. The tungsten layer is protected by the provision of a tungsten silicide cap which is formed over the tungsten layer and which therefore prevents oxidation of the metal. The two tungsten based layers are such as to replace the second polysilicon layer which is normally used to form the floating gate.
摘要翻译：为了减轻提升问题并降低堆叠的高度，在诸如ONO层的多层电介质层上形成钨层，其将导电控制栅极与多晶硅浮栅隔开，该多晶硅浮栅依次形成在隧道氧化层。通过在钨层上形成钨硅化物帽来保护钨层，从而防止金属的氧化。两个钨基层可以替代通常用于形成浮栅的第二多晶硅层。

43. 发明授权

US5994778A Surface treatment of low-k SiOF to prevent metal interaction 有权
标题翻译：表面处理低k SiOF以防止金属相互作用
公开(公告)号：US5994778A
公开(公告)日：1999-11-30
申请号：US157240
申请日：1998-09-18
申请人： Richard J. Huang , Guarionex Morales , Simon Chan
发明人： Richard J. Huang , Guarionex Morales , Simon Chan
IPC分类号： H01L21/316 , H01L23/532 , H01L23/522
CPC分类号： H01L21/02131 , H01L21/0214 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/31629 , H01L23/5329 , H01L2924/0002 , Y10S257/915
摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。进一步优选的是，处理过的表面被钝化。本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟到预定深度。

44. 发明授权

US5635423A Simplified dual damascene process for multi-level metallization and interconnection structure 失效
标题翻译：用于多层次金属化和互连结构的简化双镶嵌工艺
公开(公告)号：US5635423A
公开(公告)日：1997-06-03
申请号：US320516
申请日：1994-10-11
申请人： Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , Ming-Ren Lin
发明人： Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/7681 , H01L21/76807 , H01L21/76813
摘要： A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.
摘要翻译：通过改进的双镶嵌工艺产生包含具有减小的布线间距的互连结构的半导体器件。在一个实施例中，用于通孔的开口最初形成在第一绝缘层之上的第二绝缘层中，其间具有蚀刻停止层。然后在第二绝缘层中形成用于沟槽的较大开口，同时使通孔开口延伸穿过蚀刻停止层和第一绝缘层。沟槽和通孔然后同时填充导电材料。

45. 发明授权

US06927113B1 Semiconductor component and method of manufacture 有权
标题翻译：半导体元件及制造方法
公开(公告)号：US06927113B1
公开(公告)日：2005-08-09
申请号：US10444353
申请日：2003-05-23
申请人： Kashmir S. Sahota , Jeremy Martin , Richard J. Huang , James J. Xie
发明人： Kashmir S. Sahota , Jeremy Martin , Richard J. Huang , James J. Xie
IPC分类号： H01L21/768 , H01L21/8238 , H01L23/532
CPC分类号： H01L21/76811 , H01L21/76835 , H01L21/7684 , H01L21/76849 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask and into the dielectric layer. The opening is lined with a barrier layer and filled with an electrically conductive material. The electrically conductive material is planarized, where the planarization process stops on the barrier layer. Following planarization, the electrically conductive material is recessed using either an over-polishing process with highly selective copper slurry or a wet etching process to partially re-open the filled metal-filled trench or via. The recess process is performed such that the exposed portion of the electrically conductive material is below the dielectric layer. A capping layer is then deposited on both the dielectric portion and the exposed metal interconnect portion of the electrically conductive material.
摘要翻译：一种半导体部件和用于制造半导体部件的方法，其减轻半导体部件的金属化系统中的迁移和应力迁移。在介电层上形成硬掩模，并且通过硬掩模蚀刻开口并进入电介质层。开口衬有阻挡层并填充有导电材料。导电材料被平坦化，其中平坦化处理在阻挡层上停止。在平坦化之后，使用具有高选择性铜浆料的过度抛光工艺或湿式蚀刻工艺来使导电材料凹陷，以部分地重新打开填充的填充有金属的沟槽或通孔。执行凹陷处理，使得导电材料的暴露部分在介电层之下。然后在电介质部分和导电材料的暴露的金属互连部分上沉积覆盖层。

46. 发明授权

US06495443B1 Method of re-working copper damascene wafers 失效
标题翻译：重铜铜镶嵌晶圆的方法
公开(公告)号：US06495443B1
公开(公告)日：2002-12-17
申请号：US09874513
申请日：2001-06-05
申请人： Sergey Lopatin , Richard J. Huang
发明人： Sergey Lopatin , Richard J. Huang
IPC分类号： H01L214763
CPC分类号： H01L21/2885 , H01L21/76877 , H01L21/76892
摘要： A method of re-working a semiconductor device having a defective copper damascene interconnect structure, including the steps of obtaining a semiconductor wafer having at least one defect in a copper damascene interconnect structure; placing the wafer in an electrolyte in an electrolytic cell such that the defective copper damascene interconnect structure forms an anode; applying electrical current to the wafer to remove from the wafer substantially all copper from the defective copper damascene interconnect structure; re-applying copper to the semiconductor wafer to form a copper damascene interconnect structure.
摘要翻译：一种重新制造具有不良铜镶嵌互连结构的半导体器件的方法，包括以下步骤：获得具有铜镶嵌互连结构中的至少一个缺陷的半导体晶片; 将晶片放置在电解槽中的电解液中，使得有缺陷的铜镶嵌互连结构形成阳极; 向所述晶片施加电流以从所述晶片基本上全部铜从所述有缺陷的铜镶嵌互连结构中去除; 将铜重新施加到半导体晶片以形成铜镶嵌互连结构。

47. 发明授权

US06492258B1 METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY 有权
标题翻译：用于通过退火互连线和使用低偏置电压和低中间层介电沉积速率和半导体芯片制造来减少0.25微米和小型半导体芯片技术的应力诱发电位的方法
公开(公告)号：US06492258B1
公开(公告)日：2002-12-10
申请号：US09881831
申请日：2001-06-14
申请人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
发明人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
IPC分类号： H01L214763
CPC分类号： H01L21/7685 , H01L21/76837 , H01L21/76858 , H01L21/76885 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.
摘要翻译：制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火期间，形成铝和钛的合金，其随后容积收缩，铝的收缩被铝吸收。因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。因此，形成不希望的空隙的可能性。在互连线路中减少。在随后的ILD间隙填充沉积过程中，通过使用相对低的偏压功率来降低气相沉积温度，仍然进一步降低了不希望的空隙形成的可能性。并且通过使用相对低的源气体沉积流速来减少在ILD形成期间在互连线上的流动引起的压缩应力。

48. 发明授权

US06429108B1 Non-volatile memory device with encapsulated tungsten gate and method of making same 有权
标题翻译：具有封装钨栅的非易失性存储器件及其制造方法
公开(公告)号：US06429108B1
公开(公告)日：2002-08-06
申请号：US09652136
申请日：2000-08-31
申请人： Chi Chang , Richard J. Huang , Keizaburo Yoshie , Yu Sun
发明人： Chi Chang , Richard J. Huang , Keizaburo Yoshie , Yu Sun
IPC分类号： H01L213205
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11543 , H01L29/42324 , H01L29/66825
摘要： A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell with silicon nitride capping and sidewall layers, thereby preventing deleterious oxidation during subsequent processing at high temperature in an oxidizing ambient.
摘要翻译：通过将MOS晶体管和浮置栅极存储单元中的每一个的钨栅极电极接触封装在氮化硅封盖和侧壁层上，可制造钨栅极MOS晶体管和用于快闪EEPROM器件的存储单元，从而防止随后的处理过程中的有害氧化氧化环境中的高温。

49. 发明授权

US06361837B1 Method and system for modifying and densifying a porous film 有权
公开(公告)号：US06361837B1
公开(公告)日：2002-03-26
申请号：US09232359
申请日：1999-01-15
申请人： Suzette K. Pangrle , Richard J. Huang , Shekhar Pramanick
发明人： Suzette K. Pangrle , Richard J. Huang , Shekhar Pramanick
IPC分类号： B05D306
摘要： The invention provides a system and a method for densifying a surface of a porous film. By reducing the porosity of a film, the method yields a densified film that is more impenetrable to subsequent liquid processes. The method comprises the steps of providing a film having an exposed surface. The film can be supported by a semiconductor substrate. When the film is moved to a processing position, a focused source of radiation is created by a beam source. The exposed surface of the film is then irradiated by the beam source at the processing position until a predetermined dielectric constant is achieved. The film or beam source may be rotated, inclined, and/or moved between a variety of positions to ensure that the exposed surface of the film is irradiated evenly.

50. 发明授权

US06346467B1 Method of making tungsten gate MOS transistor and memory cell by encapsulating 有权
标题翻译：通过封装制造钨栅MOS晶体管和存储单元的方法
公开(公告)号：US06346467B1
公开(公告)日：2002-02-12
申请号：US09649027
申请日：2000-08-28
申请人： Chi Chang , Richard J. Huang , Keizaburo Yoshie , Yu Sun
发明人： Chi Chang , Richard J. Huang , Keizaburo Yoshie , Yu Sun
IPC分类号： H01L213205
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.
摘要翻译：通过用氮化硅封盖和侧壁层封装MOS晶体管和浮动栅极存储单元中的每一个的钨栅极电极接触，制造了用于快闪EEPROM器件的钨栅MOS晶体管和存储单元。本发明的方法有利地防止在高温和氧化环境中的后续处理期间的有害氧化。

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