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41. 发明申请

US20140269131A1 MEMORY WITH POWER SAVINGS FOR UNNECESSARY READS 有权
标题翻译：具有省电功能的记忆用于不必要的阅读
公开(公告)号：US20140269131A1
公开(公告)日：2014-09-18
申请号：US13826427
申请日：2013-03-14
申请人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C8/12
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译：存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号，相应的多个读出放大器之一。

42. 发明授权

US08755244B2 Write contention-free, noise-tolerant multi-port bitcell 有权
标题翻译：写入无争用，耐噪声的多端口位单元
公开(公告)号：US08755244B2
公开(公告)日：2014-06-17
申请号：US13441414
申请日：2012-04-06
申请人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C8/00 , G11C11/00
CPC分类号： G11C8/16 , G11C7/12 , G11C7/18 , G11C8/14 , G11C11/419
摘要： A multi-port memory cell of a multi-port memory array includes a first inverter that inverter is disabled by a first subset of write word lines and a second inverter, cross coupled with the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter. The second selection circuit has data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter.
摘要翻译：多端口存储器阵列的多端口存储单元包括第一反相器，反相器被写入字线的第一子集禁止，第二反相器与第一反相器交叉耦合，其中第二反相器被第二反相器禁用多个写入字线的子集。第一选择电路具有耦合到多个写位线的第一子集的数据输入，耦合到多个写字线的第一子集的选择输入以及耦合到第二反相器的输入的输出。第二选择电路具有耦合到多个写位线的第二子集的数据输入，耦合到多个写字线的第二子集的选择输入以及耦合到第一反相器的输入的输出。

43. 发明授权

US08677205B2 Hierarchical error correction for large memories 有权
标题翻译：大存储器的分层纠错
公开(公告)号：US08677205B2
公开(公告)日：2014-03-18
申请号：US13045307
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
发明人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
IPC分类号： H03M13/00
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access.
摘要翻译：提供了一种用于检测和校正存储在正在读取的存储器区域中的数据段中的第一数量的位错误的机制，同时检测该数据段中是否存在较高数量的位错误。在存储器区域的任何单个数据段中检测到较高数量的位错误的情况下，对存储器区域执行该更高数量的位错误的错误校正，同时检测存在更高级别的位错误。通过以这样的分级顺序执行更高级别的比特错误的纠错，可以在大多数数据访问中避免与这种纠错相关联的存储器等待时间，从而提高数据访问的性能。

44. 发明授权

US08587356B2 Recoverable and reconfigurable pipeline structure for state-retention power gating 有权
标题翻译：用于状态保持功率门控的可恢复和可重新配置的管道结构
公开(公告)号：US08587356B2
公开(公告)日：2013-11-19
申请号：US13403597
申请日：2012-02-23
申请人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
发明人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
IPC分类号： H03K3/00
CPC分类号： H03K3/35606 , H03K3/356008
摘要： A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode.
摘要翻译：公开了一种系统，电子电路和方法。方法实施例包括接收与电子电路的电源门控操作模式相关联的控制信号，基于电源门控操作模式将参考电压施加到电子电路，以及维护表示电子电路的逻辑级状态的数据基于电源门控操作模式。在所描述的实施例中，维护包括在第一电源门控操作模式中将电子电路的第一逻辑级的状态的数据存储在第一存储元件内，以及恢复电子电路的第二逻辑级的状态的数据在第二电源门控操作模式中利用第一存储元件内的电子电路的第一逻辑级的状态的数据。

45. 发明授权

US08533578B2 Error detection in a content addressable memory (CAM) and method of operation 有权
标题翻译：内容可寻址存储器（CAM）中的错误检测和操作方法
公开(公告)号：US08533578B2
公开(公告)日：2013-09-10
申请号：US12813974
申请日：2010-06-11
申请人： Ravindraraj Ramaraju , Ambica Ashok , Kent W. Li
发明人： Ravindraraj Ramaraju , Ambica Ashok , Kent W. Li
IPC分类号： G11C29/00
CPC分类号： G11C15/04 , G06F11/1064 , H03M13/09
摘要： A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.
摘要翻译：一种用于访问具有CAM和随机存取存储器（RAM）的内容可寻址存储器（CAM）系统的方法，包括向CAM提供比较数据，将比较数据与CAM的条目进行比较，以确定匹配的CAM条目并确定匹配信号对应于匹配的CAM条目。响应于确定匹配信号，该方法还包括使用比较数据从RAM提供输出数据，输出奇偶校验位和输出补码奇偶校验位，以产生生成的奇偶校验位，并且基于产生的奇偶校验位，输出奇偶校验位和输出补码奇偶校验位。当产生的奇偶校验位不等于输出奇偶校验位时，或当输出奇偶校验位等于输出补码奇偶校验位时，错误指示器可能指示错误。

46. 发明授权

US08493121B1 Reconfigurable flip-flop 有权
公开(公告)号：US08493121B1
公开(公告)日：2013-07-23
申请号：US13605385
申请日：2012-09-06
申请人： Ravindraraj Ramaraju
发明人： Ravindraraj Ramaraju
IPC分类号： H03K3/356
CPC分类号： H03K3/3568 , H03K3/356156
摘要： A device (300, 1000) provides a dual-edge triggered flip-flop (DETFF) that is reconfigurable to a master-slave flip-flop (MSFF). The device includes a reconfigurable MUX-D flip-flop including two distinct circuit configurations. In a first configuration, two latches or storage elements (340, 360, 1040, 1060) are operating in series to provide a MUX-D flip-flop. In a second configuration, the storage elements (340, 360, 1040, 1060) are operating in parallel to provide a dual-edge triggered flip-flop (DETFF).

47. 发明授权

US08099580B2 Translation look-aside buffer with a tag memory and method therefor 有权
标题翻译：具有标签记忆的翻译后备缓冲器及其方法
公开(公告)号：US08099580B2
公开(公告)日：2012-01-17
申请号：US12480809
申请日：2009-06-09
申请人： Ravindraraj Ramaraju , Jogendra C. Sarker , Vu N. Tran
发明人： Ravindraraj Ramaraju , Jogendra C. Sarker , Vu N. Tran
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0895
摘要： A translation look-aside buffer (TLB) has a TAG memory for determining if a desired translated address is stored in the TLB. A TAG portion is compared to contents of the TAG memory without requiring a read of the TAG memory because the TAG memory has a storage portion that is constructed as a CAM. For each row of the CAM a match determination is made that indicates if the TAG portion is the same as contents of the particular row. A decoder decodes an index portion and provides an output for each row. On a per row basis the output of the decoder is logically combined with the hit/miss signals to determine if there is a hit for the TAG memory. If there is a hit for the TAG memory, a translated address corresponding to the index portion of the address is then output as the selected translated address.
摘要翻译：翻译后备缓冲器（TLB）具有用于确定所需翻译地址是否存储在TLB中的TAG存储器。将TAG部分与TAG存储器的内容进行比较，而不需要读取TAG存储器，因为TAG存储器具有构造为CAM的存储部分。对于CAM的每一行，进行匹配确定，其指示TAG部分是否与特定行的内容相同。解码器解码索引部分并为每行提供输出。在每行的基础上，解码器的输出与命中/未命中信号逻辑地组合以确定是否存在对TAG存储器的命中。如果存在TAG存储器的命中，则将与地址的索引部分相对应的翻译地址作为选择的翻译地址输出。

48. 发明申请

US20110239069A1 SEQUENTIAL DIGITAL CIRCUITRY WITH TEST SCAN 有权
标题翻译：具有测试扫描的连续数字电路
公开(公告)号：US20110239069A1
公开(公告)日：2011-09-29
申请号：US12729826
申请日：2010-03-23
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare , Gray A. Mussemann , Mihir S. Sabnis
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare , Gray A. Mussemann , Mihir S. Sabnis
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/267 , G01R31/318541 , G01R31/318575
摘要： A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.
摘要翻译：具有测试扫描的数字扫描链系统具有多个触发器模块，多个触发器模块中的每一个具有第一数据位输入，第二数据位输入，测试位输入，时钟输入，第一数据位输出，第二数据位输出和测试位输出。第一触发器模块的测试位输出直接连接到第二触发器模块的测试位输入，而没有中间电路。第一和第二复用主/从触发器直接串行连接。时钟锁存器耦合到第二复用主/从触发器的输出并提供测试位输出。时钟锁存器仅在测试模式下计时才能节省电量。

49. 发明申请

US20110194325A1 ERROR DETECTION IN A CONTENT ADDRESSABLE MEMORY (CAM) 有权
标题翻译：内容可寻址存储器中的错误检测（CAM）
公开(公告)号：US20110194325A1
公开(公告)日：2011-08-11
申请号：US12703528
申请日：2010-02-10
申请人： Ravindraraj Ramaraju , Michael D. Snyder
发明人： Ravindraraj Ramaraju , Michael D. Snyder
IPC分类号： G11C15/00 , G11C29/00
CPC分类号： G11C15/04 , G06F11/1064 , G11C29/52
摘要： A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit.
摘要翻译：内容可寻址存储器和操作方法使用具有多行存储的内容可寻址存储器数据的存储器阵列和用于将接收到的比较数据与存储的内容可寻址存储器数据进行比较的比较电路。为每行提供命中信号和一个或多个奇偶校验位。耦合到每行的存储器阵列的错误的命中检测电路响应于比较数据的奇偶性与与命中信号相关联的行的奇偶校验之间的比较，产生行错误指示，如通过断言该命中信号的命中信号行。错误的命中检测电路使用每一行的行错误指示符来提供指示至少一个被断言的命中信号是否对应于错误命中的输出。

50. 发明申请

US20110095800A1 FLIP-FLOP HAVING SHARED FEEDBACK AND METHOD OF OPERATION 有权
标题翻译：具有共享反馈的翻转和操作方法
公开(公告)号：US20110095800A1
公开(公告)日：2011-04-28
申请号：US12607574
申请日：2009-10-28
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare
IPC分类号： H03K3/356 , H03K3/00
CPC分类号： H03K3/356156 , H03K3/356173
摘要： A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a third node to couple the first data signal to the third node. The first node is decoupled from the second node and a first step of latching the first data signal at the third node is performed, wherein the first step of latching is through the second node while the second node is coupled to the third node. The second node is decoupled from the third node and a second step of latching is performed wherein the first data signal latched at the third node while the second node is decoupled from the third node.
摘要翻译：一种操作电路的方法包括在第一节点处接收第一数据信号。第一节点耦合到第二节点以将第一数据信号耦合到第二节点。在将第一节点耦合到第二节点之后，第二节点耦合到第三节点以将第一数据信号耦合到第三节点。执行第一节点与第二节点的耦合，并且执行在第三节点处锁存第一数据信号的第一步骤，其中锁定的第一步骤是通过第二节点，而第二节点耦合到第三节点。第二节点与第三节点分离，并执行锁定的第二步骤，其中第一数据信号在第三节点处锁存，而第二节点与第三节点分离。

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