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41. 发明授权

US06759702B2 Memory cell with vertical transistor and trench capacitor with reduced burried strap 有权
标题翻译：具有垂直晶体管和沟槽电容器的存储单元，具有减少的挂带
公开(公告)号：US06759702B2
公开(公告)日：2004-07-06
申请号：US10261559
申请日：2002-09-30
申请人： Carl J. Radens , Ramachandra Divakaruni , Jack A. Mandelman
发明人： Carl J. Radens , Ramachandra Divakaruni , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/66181 , H01L29/945
摘要： A memory cell structure including a semiconductor substrate, a deep (e.g., longitudinal) trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom, a buried strap along a sidewall of the deep trench, a storage capacitor at the bottom of the deep trench, a vertical transistor extending down the sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench, a collar oxide extending down another sidewall of the deep trench opposite the capacitor, shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends, a gate conductor extending within the deep trench, a wordline extending over the deep trench and connected to the gate conductor, and a bitline extending above the surface plane of the substrate having a contact to the diffusion between the shallow trench isolation regions. The deep trench has a perimeter in a direction normal to its depth, and the buried strap extends a distance along the perimeter, the distance being only within a range of 5% to 20% of the entire linear distance along the perimeter, and being less than one lithographic feature size. Preferably, the strap in a direction along the perimeter is curved and is disposed along only one corner of the perimeter. The structure is particularly useful for a sub-8F2 cell.
摘要翻译：一种存储单元结构，包括半导体衬底，半导体衬底中的深（例如，纵向）沟槽，深沟槽具有多个侧壁和底部，沿着深沟槽的侧壁的掩埋带，存储电容器深沟槽的底部，垂直晶体管，沿着存储电容器上方的深沟槽的侧壁向下延伸，晶体管具有在衬底的与深沟槽相邻的平面中延伸的扩散，从深沟槽的另一个侧壁延伸的环状氧化物与电容器相对的浅沟槽隔离区域沿垂直于垂直晶体管延伸的侧壁横向的衬底表面延伸，在深沟槽内延伸的栅极导体，延伸在深沟槽上并与栅极导体连接的字线以及在衬底的表面平面上方延伸的位线，该位线与浅沟槽iso之间的扩散接触国际地区。深沟槽在垂直于其深度的方向上具有周长，并且掩埋带沿着周边延伸一段距离，该距离仅在沿着周边的整个线性距离的5％至20％的范围内，并且更小比一个光刻特征尺寸。优选地，沿着周边的方向上的带子是弯曲的并且沿着周边的一个角部设置。该结构对于亚8F 2细胞特别有用。

42. 发明授权

US06750097B2 Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby 有权
标题翻译：制造具有由此形成的垂直器件单元和器件的平板SOI嵌入式DRAM / eDRAM的方法
公开(公告)号：US06750097B2
公开(公告)日：2004-06-15
申请号：US10210632
申请日：2002-07-30
申请人： Ramachandra Divakaruni , Jack A. Mandelman
发明人： Ramachandra Divakaruni , Jack A. Mandelman
IPC分类号： H01L218242
CPC分类号： H01L27/10897 , H01L27/10864 , H01L27/1203
摘要： Disclosed herein is a patterned silicon-on-insulator (SOI) method of fabricating a combined integrated circuit having both a logic portion and an embedded dynamic random access memory (DRAM) array portion. The disclosed method includes masking an array portion of a substrate with a first mask, implanting oxygen to form a buried oxide layer in a logic portion of the substrate not masked by the first mask, depositing and patterning a second mask over the array portion and the logic portion, and etching isolation trenches in the array portion and the logic portion, the isolation trenches defined by openings in the patterned second mask. The first mask may additionally protect the array portion when rounding device corners in the logic portion. The second mask may additionally protect the logic portion when performing implants in the array portion. An integrated circuit formed on a single substrate is disclosed herein including at least one SOI device having a rounded corner and at least one DRAM cell having a vertical pass gate, wherein the DRAM cell is formed on a bulk portion of the substrate.
摘要翻译：本文公开了一种制造具有逻辑部分和嵌入式动态随机存取存储器（DRAM）阵列部分的组合集成电路的图案化的绝缘体上硅（SOI）方法。所公开的方法包括用第一掩模掩蔽衬底的阵列部分，注入氧以在未被第一掩模掩蔽的衬底的逻辑部分中形成掩埋氧化物层，在阵列部分上沉积和图案化第二掩模，逻辑部分和在阵列部分和逻辑部分中的蚀刻隔离沟槽，隔离沟槽由图案化的第二掩模中的开口限定。当对逻辑部分中的设备角进行舍入时，第一掩模可以附加地保护阵列部分。当在阵列部分中执行植入时，第二掩模可以附加地保护逻辑部分。本文公开了形成在单个基板上的集成电路，其包括具有圆角的至少一个SOI器件和具有垂直通过栅极的至少一个DRAM单元，其中所述DRAM单元形成在所述衬底的主体部分上。

43. 发明授权

US06642566B1 Asymmetric inside spacer for vertical transistor 失效
标题翻译：垂直晶体管的不对称内隔板
公开(公告)号：US06642566B1
公开(公告)日：2003-11-04
申请号：US10195601
申请日：2002-06-28
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Haining Yang
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Haining Yang
IPC分类号： H01L2708
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10888 , H01L27/10891
摘要： A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wider connection between the wordline and the transistor electrode and using the wordline as an etch stop to protect the transistor gate during the patterning of the wordlines.
摘要翻译：具有使用垂直晶体管的DRAM单元的DRAM阵列通过在字线和晶体管之间的连接中使用不对称结构来增加电可靠性并降低位线电容，从而允许在字线和晶体管电极之间使用更宽的连接并且使用该字线作为蚀刻停止以在图形化字线期间保护晶体管栅极。

44. 发明授权

US06518118B2 Structure and process for buried bitline and single sided buried conductor formation 失效
公开(公告)号：US06518118B2
公开(公告)日：2003-02-11
申请号：US09808799
申请日：2001-03-15
申请人： Satish D. Athavale , Ramachandra Divakaruni , Jack A. Mandelman
发明人： Satish D. Athavale , Ramachandra Divakaruni , Jack A. Mandelman
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/10885
摘要： Semiconductor devices generally, and in particular DRAM memory devices, having buried, single-sided conductors are provided. Additionally, methods of fabricating semiconductor devices having buried, single-sided conductors are provided.

45. 发明授权

US06444548B1 Bitline diffusion with halo for improved array threshold voltage control 有权
公开(公告)号：US06444548B1
公开(公告)日：2002-09-03
申请号：US09257817
申请日：1999-02-25
申请人： Ramachandra Divakaruni , Yujun Li , Jack A. Mandelman
发明人： Ramachandra Divakaruni , Yujun Li , Jack A. Mandelman
IPC分类号： H01L218242
摘要： A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.

46. 发明授权

US06339241B1 Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch 有权
公开(公告)号：US06339241B1
公开(公告)日：2002-01-15
申请号：US09602426
申请日：2000-06-23
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.

47. 发明申请

US20090047756A1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 失效
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：US20090047756A1
公开(公告)日：2009-02-19
申请号：US12254960
申请日：2008-10-21
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

48. 发明授权

US07459743B2 Dual port gain cell with side and top gated read transistor 有权
标题翻译：双端口增益单元，具有侧和顶栅控读取晶体管
公开(公告)号：US07459743B2
公开(公告)日：2008-12-02
申请号：US11161962
申请日：2005-08-24
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

49. 发明授权

US06777737B2 Vertical DRAM punchthrough stop self-aligned to storage trench 有权
标题翻译：垂直DRAM穿透停止自对准到存储沟槽
公开(公告)号：US06777737B2
公开(公告)日：2004-08-17
申请号：US10016605
申请日：2001-10-30
申请人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
发明人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10885 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.
摘要翻译：具有小于约90nm的特征尺寸的显示器很少或没有动态电荷损失并且很少或没有陷阱辅助结漏电的半导体存储器结构被提供。具体地，半导体结构包括存在于含Si衬底中的至少一个背靠背对的沟槽存储存储单元。每个存储单元包括覆盖沟槽电容器的垂直晶体管。在沟槽存储单元的每个垂直侧壁上都存在带外扩散，以将每个存储单元的垂直晶体管和沟槽电容器互连到含Si衬底。穿通阻止掺杂袋位于每个背对背对的沟槽存储存储单元之间，并且其位于相邻存储沟槽的带外扩展之间并且与相邻存储沟槽自对准。

50. 发明授权

US06759291B2 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06759291B2
公开(公告)日：2004-07-06
申请号：US10045499
申请日：2002-01-14
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L218234
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

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