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    • 44. 发明公开
    • SUPER-JUNCTION-SCHOTTKY-PIN-DIODE
    • 超结肖特基-PIN二极管
    • EP2740155A1
    • 2014-06-11
    • EP12737284.5
    • 2012-07-19
    • Robert Bosch GmbH
    • QU, NingGOERLACH, Alfred
    • H01L29/06H01L29/872H01L21/329
    • H01L29/0634H01L29/0649H01L29/66143H01L29/868H01L29/872
    • The invention relates to a semiconductor chip that comprises an n
      + -doped substrate, above which an n-doped epilayer comprising trenches inserted in the epilayer that are filled with p-doped semiconductor material and that in each case have a highly p-doped area on the upper side thereof, is located in such a way that an alternating arrangement of n-doped areas having a first width and p-doped areas having a second width is present. The chip further comprises a first metal layer that is provided on the front side thereof, which metal layer forms a Schottky contact with the n-doped epilayer and an ohmic contact with the highly p-doped areas and serves as an anode electrode. A second metal layer is provided on the rear side of the semiconductor chip, which layer presents an ohmic contact and serves as a cathode electrode. A dieletric layer is provided in each case between an n-doped area and an adjacent p-doped area.
    • 半导体芯片具有n +掺杂的衬底,其上引入具有沟槽的n掺杂外延层,沟槽被p掺杂半导体材料填充,并且在每种情况下在其顶侧具有高度p掺杂区域,使得 存在具有第一宽度的n掺杂区域和具有第二宽度的p掺杂区域的交替布置。 用作阳极的第一金属层设置在芯片的正面,并与n掺杂的外延层形成肖特基接触,并与高p掺杂区形成欧姆接触。 表示欧姆接触并用作阴极的第二金属层形成在半导体芯片的后侧。 在每个n掺杂区域和相邻的p掺杂区域之间提供介电层。