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41. 发明申请

US20120286337A1 FIN FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： FIN场效应晶体管及其制造方法
公开(公告)号：US20120286337A1
公开(公告)日：2012-11-15
申请号：US13377141
申请日：2011-08-10
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L27/1211 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L29/66545
摘要： Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.
摘要翻译：本发明的实施例公开了一种制造Fin场效应晶体管的方法。当形成翅片时，在翅片上形成跨鳍片的虚拟栅极，在虚拟栅极的侧壁上形成间隔物，并且在第一介电层上形成覆盖层，并在模拟栅极外部形成覆盖层，然后，通过间隔物在伪栅极的两侧形成自对准和升高的源/漏区，其中栅极和源极/漏极区的上表面在同一平面内。栅极和源极/漏极区域的上表面位于相同的平面中，使接触插塞的对准更容易; 并且栅极和源极/漏极区域被间隔物分开，从而提高对准精度，解决接触插塞的不准确的对准以及提高器件AC性能。

42. 发明申请

US20120187496A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120187496A1
公开(公告)日：2012-07-26
申请号：US13266555
申请日：2011-04-19
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/302
CPC分类号： H01L29/66636 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
摘要翻译：一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。还提供了半导体器件。可以减小隔离区域的面积。

43. 发明申请

US20120043624A1 ULTRA-THIN BODY TRANSISTOR AND METHOD FOR MANUFCTURING THE SAME 审中-公开
标题翻译：超薄体晶体管及其制造方法
公开(公告)号：US20120043624A1
公开(公告)日：2012-02-23
申请号：US13132535
申请日：2011-01-27
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78654 , H01L21/28123 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/7834
摘要： An ultra-thin body transistor and a method for manufacturing an ultra-thin body transistor are disclosed. The ultra-thin body transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source region and a drain region in the semiconductor substrate and on either side of the gate structure; in which the gate structure comprises a gate dielectric layer, a gate embedded in the gate dielectric layer, and a spacer on both sides of the gate; the ultra-thin body transistor further comprises: a body region and a buried insulated region located sequentially under the gate structure and in a well region; two ends of the body region and the buried insulated region are connected with the source region and the drain region respectively; and the body region is isolated from other regions in the well region by the buried insulated region under the body region. The ultra-thin body transistor has a thinner body region, which decreases the short channel effect. In the method for manufacturing an ultra-thin body transistor together with the replacement-gate process, the forming of the buried insulated region is self-aligned with the gate, which reduces the parasitic resistance under the spacer.
摘要翻译：公开了一种超薄体晶体管和制造超薄体晶体管的方法。超薄体晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及半导体衬底中的栅极结构的任一侧上的源极区和漏极区; 其中栅极结构包括栅极电介质层，嵌入栅极电介质层中的栅极和栅极两侧的间隔物; 所述超薄体晶体管还包括：主体区域和位于所述栅极结构之下且位于阱区域中的掩埋绝缘区域; 主体区域和埋入绝缘区域的两端分别与源极区域和漏极区域连接; 并且身体区域通过身体区域下的埋入绝缘区域与阱区域中的其它区域隔离。超薄体晶体管具有较薄的体区，从而降低了短沟道效应。在与替换栅极工艺一起制造超薄体晶体管的方法中，掩埋绝缘区域的形成与栅极自对准，这降低了间隔物下的寄生电阻。

44. 发明申请

US20090073758A1 SRAM CELLS WITH ASYMMETRIC FLOATING-BODY PASS-GATE TRANSISTORS 审中-公开
标题翻译：具有不对称浮动体态栅极晶体管的SRAM电池
公开(公告)号：US20090073758A1
公开(公告)日：2009-03-19
申请号：US11857757
申请日：2007-09-19
申请人： Gregory G. Freeman , Qingqing Liang , Mario M. Pelella , Carl J. Radens , Huicai Zhong , Huilong Zhu
发明人： Gregory G. Freeman , Qingqing Liang , Mario M. Pelella , Carl J. Radens , Huicai Zhong , Huilong Zhu
IPC分类号： G11C11/34 , H01L21/00
CPC分类号： G11C11/412
摘要： The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.
摘要翻译：本发明的实施例提供具有非对称浮体通过栅极晶体管的SRAM单元。更具体地，半导体器件包括SRAM单元，第一通过栅极晶体管和第二通过栅极晶体管。第一栅极晶体管连接到SRAM单元的第一侧，其中第一栅极晶体管包括第一漏极区域和第一源极区域。第二通栅晶体管连接到SRAM单元的第二侧，其中第二侧与第一侧相对。第二通栅晶体管包括第二源区和第二漏区。此外，第一源区和/或第二源区包括氙植入物。第一漏区和第二漏区各自缺少氙植入物。

45. 发明授权

US08779514B2 Transistor and method for manufacturing the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US08779514B2
公开(公告)日：2014-07-15
申请号：US13144903
申请日：2011-02-25
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78648 , H01L29/66545 , H01L29/66628
摘要： The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.
摘要翻译：本发明涉及晶体管及其制造方法。根据本发明的实施例的晶体管可以包括：至少包括晶体管的背栅极，绝缘层和顺序层叠的半导体层的衬底，其中晶体管的背栅极用于调节晶体管的阈值电压晶体管; 形成在所述半导体层上的栅极堆叠，其中所述栅极堆叠包括形成在所述栅极电介质上的栅极电介质和栅电极; 形成在栅叠层的侧壁上的间隔物; 以及分别位于栅极堆叠的两侧的源极区域和漏极区域，其中栅极叠层的高度低于间隔物的高度。该晶体管能够降低栅极叠层的高度，从而提高晶体管的性能。

46. 发明授权

US08592911B2 Asymmetric semiconductor device having a high-k/metal gate and method of manufacturing the same 有权
标题翻译：具有高k /金属栅极的非对称半导体器件及其制造方法
公开(公告)号：US08592911B2
公开(公告)日：2013-11-26
申请号：US13063717
申请日：2010-09-25
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L21/28105 , H01L21/2815 , H01L21/823462 , H01L21/823468 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66659
摘要： A semiconductor device and a method of manufacturing the same are provided. The semiconductor device has a metal sidewall spacer on the sidewall of a gate electrode on the drain region side. The metal sidewall spacer is made of such metals as Ta, which has an oxygen scavenging effect and can effectively reduce EOT on the drain region side, and thus the ability to control the short channel is effectively increased. In addition, since EOT on the source region side is larger, the carrier mobility of the device will not be degraded. Moreover, such asymmetric device may have a better driving performance.
摘要翻译：提供半导体器件及其制造方法。半导体器件在漏极区侧的栅电极的侧壁上具有金属侧壁间隔物。金属侧壁间隔物由具有除氧效果的Ta等金属制成，能够有效地减少漏区侧面的EOT，有效地提高控制短路的能力。此外，由于源区域侧的EOT较大，所以器件的载流子迁移率不会降低。此外，这种不对称装置可能具有更好的驱动性能。

47. 发明授权

US08557677B2 Stack-type semiconductor device and method for manufacturing the same 有权
标题翻译：叠层型半导体器件及其制造方法
公开(公告)号：US08557677B2
公开(公告)日：2013-10-15
申请号：US13120792
申请日：2011-02-17
申请人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.
摘要翻译：堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合通过导电通孔。这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高可靠性的三维半导体器件。

48. 发明申请

US20130140624A1 Semiconductor Structure and Method for Forming The Semiconductor Structure 有权
标题翻译：用于形成半导体结构的半导体结构和方法
公开(公告)号：US20130140624A1
公开(公告)日：2013-06-06
申请号：US13807010
申请日：2011-11-30
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/28008 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11556 , H01L27/1203 , H01L29/458 , H01L29/4908 , H01L29/66666 , H01L29/78642
摘要： The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.
摘要翻译：本发明公开了一种半导体结构，包括：衬底，导体层和围绕衬底上的导体层的电介质层; 覆盖所述导体层和所述电介质层的第一绝缘层; 形成在第一绝缘层上的栅极导体层和围绕栅极导体层的电介质层; 以及覆盖所述栅极导体层和围绕所述栅极导体层的所述电介质层的第二绝缘层; 其中填充有半导体材料的通孔垂直地穿过栅极导体层，通孔的底部停在导体层上，并且用作漏极/源极的第一导体插塞设置在通孔的顶部 ; 和用作源/漏电极的第二导体插头与导体层电接触，并且用作栅电极的第三导体插头电接触栅极导体层。

49. 发明授权

US08410609B2 Semiconductor device having carbon nanotube interconnects contact deposited with different orientation and method for manufacturing the same 有权
标题翻译：具有不同取向沉积的碳纳米管互连的半导体器件及其制造方法
公开(公告)号：US08410609B2
公开(公告)日：2013-04-02
申请号：US13129321
申请日：2011-02-26
申请人： Huicai Zhong , Qingqing Liang , Zhijiong Luo , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/40 , H01L21/00
CPC分类号： H01L23/53276 , H01L21/76807 , H01L21/76843 , H01L21/76846 , H01L21/76847 , H01L21/76877 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. The conductive layer of the structure has better thermal conductivity, conductivity and high anti-electromigration capability, thus is able to effectively prevent metal ions from diffusing outwards.
摘要翻译：半导体器件结构及其制造方法技术领域本发明涉及半导体器件结构及其制造方法。该结构包括：其上形成有器件结构的半导体衬底; 在所述器件结构上形成的层间电介质层，其中在所述层间介质层中形成沟槽，所述沟槽包括并入的通孔沟槽和导电布线沟槽，并且所述导电布线沟槽位于所述通孔沟槽上; 以及填充在所述沟槽中的导电层，其中所述导电层与所述器件结构电连接; 其中所述导电层包括由所述导电材料包围的导电材料和纳米管/线层。其中，导电层包括由导电材料包围的导电材料和纳米管/线层。该结构的导电层具有较好的导热性，导电性和较高的抗电迁移能力，能有效防止金属离子向外扩散。

50. 发明申请

US20130015526A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130015526A1
公开(公告)日：2013-01-17
申请号：US13380806
申请日：2011-08-09
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7849 , H01L21/823807 , H01L21/84 , H01L27/1203
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明实施例的半导体器件包括：基底，其包括基底层，基底层上的绝缘层和绝缘层上的半导体层; 以及形成在所述衬底上的第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管通过形成在所述衬底中的沟槽隔离结构彼此隔离。其中在第一和第二晶体管中的至少一个晶体管下方的基底层的至少一部分被应变，并且基底层的应变部分与绝缘层相邻。根据本发明的半导体器件增加了器件的速度，从而提高了器件的性能。

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